614 IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, VOL. 9, NO. 2, MARCH/APRIL 2003 Optical Interconnects: Out of the Box Forever? Dawei Huang, Member, IEEE, Theresa Sze, Member, IEEE, Anders Landin, Rick Lytel, Member, IEEE, and Howard L. Davidson, Senior Member, IEEE Invited Paper Abstract—Based on a variety of optimization criteria, recent re- search has suggested that optical interconnects are a viable alter- native to electrical interconnects for board-to-board, chip-to-chip, and on-chip applications. However, the design of modern high-per- formance computing systems must account for a variety of perfor- mance scaling factors that are not included in these analyses. We will give an overview of the performance scaling that has driven current computer design, with a focus on architectural de- sign and the effects of these designs on interconnect implementa- tion. We then discuss the potential of optics at each of these inter- connect levels, in the context of extant electrical technology. Index Terms—Cache memories, data busses, high-speed elec- tronics, optical interconnections. I. INTRODUCTION O PTICAL INTERCONNECTS outperform electrical in- terconnects for long-distance applications. Even for dis- tances as short as 300 meters (m) at bandwidths over 1 Gb/s, fiber is now the default interconnect choice. Recent research [1]–[7] has also suggested that optics has clear advantages even at very short distances, yet optical interconnects are not common in computers. The reason optical interconnects are not widely implemented in modern computing systems is due to computer architecture design and how interconnects are balanced within those con- straints. We will discuss these issues in this paper and explain that despite the fact that optical interconnects have clear ad- vantages in time of flight and bandwidth density, these are not the only design constraints that must be considered. As a consequence, the overall optimization of modern computers has generally precluded the use of highly integrated optical interconnects. We will discuss the historical scaling of logic, memory, and wires, analyze access time and density of dynamic random access memory (DRAM), walk through the steps and timing relations for memory access, and estimate the capa- bilities of electrical interconnects at several levels. With this background, we shall characterize what would be required for optical interconnects to displace wires at the backplane, board, and chip level. Manuscript received November 22, 2002; revised February 7, 2003. D. Huang, T. Sze, and R. Lytel are with Sun Microsystems, San Diego, CA 92121 USA. A. Landin and H. L. Davidson are with Sun Microsystems, Menlo Park, CA 94025 USA (e-mail: hld@sun.com). Digital Object Identifier 10.1109/JSTQE.2003.812506 Fig. 1. Access time (nanoseconds) and density (megabit/chip) for commodity DRAM chips by year of introduction. (Note: T_Row_Cycle is the row cycle time for DRAM, which determines the memory access time and latency). II. A SHORT TOUR OF COMPUTER DESIGN A. Scaling Overview Power laws compactly express important properties of many natural and engineered systems [8]–[10]. We assert that there are three key empirical-power law scaling relationships for com- puter systems: 1) You can have twice as many transistors for your next de- sign (Moore’s law). 2) A processor should have at least enough memory that it takes one second to touch every word (Amdahl’s law). 3) There are many more short wires than long wires (Rent’s rule). These laws guide the design of successful computers. Logic, memory, and wires respond very differently to scaling down minimum feature size. Approximately, logic speed in- creases exponentially, memory density increases exponentially, and wires are sensitive to ratios of physical dimensions. The clock cycle for microprocessors has decreased from 1 s for early 8-bit chips, to 333 ps for recent designs. DRAM density has increased from 1 kb/chip to 1 Gb/chip, while raw DRAM access time has decreased from about 1.2 s to 50 ns. Fig. 1 illustrates the scaling of DRAM access time and chip density over time. When normalized to processor clock cycles, access time to a main memory built with DRAM chips is becoming ex- ponentially worse with lithographic scaling, and the number of 1077-260X/03$17.00 © 2003 IEEE