Impact of Negative-Bias-Temperature-Instability on Channel Bulk of Polysilicon TFT by Gated PIN Diode Analysis Chen-Shuo Huang a and Po-Tsun Liu b,z a Department of Photonics and Institute of Electro-Optical Engineering, and b Department of Photonics and Display Institute, National Chiao Tung University, Hsin-Chu 30010, Taiwan In this study, negative-bias-temperature-instability (NBTI) stress induced interface, and bulk states of polycrystalline silicon (poly-Si) film were identified by using gated poly-Si P-intrinsic-N (PIN) diodes. The generation of reverse current was proportional to the quantity of defects in the poly-Si of the gated diode device. Experimental results revealed NBTI degradation has a spatial distribution in the poly-Si film and demonstrated that the resultant generation of poly-Si bulk states causes the elevated drain leakage current of thin-film transistors (TFTs). We conclude that grain boundaries, with enriched hydrogenated silicon bonds in the bulk of poly-Si, interact electrochemically with hole-carriers. V C 2011 The Electrochemical Society. [DOI: 10.1149/1.3551463] All rights reserved. Manuscript submitted October 25, 2010; revised manuscript received January 6, 2011. Published February 22, 2011. Polycrystalline silicon thin-film transistors (poly-Si TFTs) are widely used as switch and driving devices in active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs). These poly-Si TFTs are suitable for multifunctional displays, because they enable the integration of driver electronics, sensors, memories, and periph- eral circuits on glass substrates, to afford system-on-panel (SOP) displays. Complementary poly-Si TFTs operate with high duty cycles in peripheral driving circuit applications and thus TFTs would suffer long-term negative and positive bias stress at elevated ambient temperatures. Negative-bias-tempera- ture-instability (NBTI) is a critical reliability issue for metal- oxide-semiconductor field-effect transistors (MOSFETs), with single-crystal silicon, also particularly for p-MOSFETs. It was reported that the electrochemical reaction between hydrogen- ated trivalent Si (Si–H) bonds and accumulated holes triggers NBTI degradation, causing the formation of interface states and positive fixed charges. 1,2 Recently, the effects of NBTI on p-channel poly-Si TFTs have attracted much research interest. One group reported that grain boundaries with many Si–H bonds experience a greater NBTI degradation than usual degra- dation. 3–5 Both the Levinson and Proano method 3 and charge pumping method 6 provide the estimation of grain boundary traps. The presence of interface states complicates the calcula- tion of grain boundary traps, additionally; the estimation applies only to a channel region just beneath the gate insulator. Thus, it is hard to investigate the grain boundary properties of poly-Si bulk under NBTI stress any further. Gated diodes are generally used to distinguish the interface trap states from bulk trap states in the single-crystal MOSFET technology. 7 How- ever, the gated diodes were little used for the investigation of NBTI effects on the poly-Si. In this work, we used the gated P-intrinsic-N (PIN) diodes to investigate defect formation in the poly-Si bulk under NBTI stress, by analysing the reverse defect-generation current. Experimental The top gate p-channel poly-Si TFT were fabricated on a Corn- ing 1737 glass substrate. First, the buffer nitride/oxide layer and then a 50-nm thick a-Si:H film were deposited by plasma-enhanced chemical vapor deposition (PECVD) at 380  C. The a-Si:H film was dehydrogenated in a furnace at 450  C for 60 min. The dehydrogen- ated a-Si was sequentially crystallized by XeCl excimer laser irradi- ation with a wavelength of 308 nm at 350 mJ/cm 2 . Microlithography and plasma dry etching processes were used to pattern the active poly-Si region, and then a 100-nm thick TEOS (Tetraethyl Orthosi- licate) base oxide film was formed as a gate insulator layer. It was followed that a layer of Mo thin film was sputter deposited and pat- terned as the gate electrode. The formation of source/drain regions was self-aligned by born implantation process through the metal gate electrode as a mask with a dosage of 8  10 14 cm 2 . Dopant activation was performed by rapid thermal annealing at 580  C for 60 s. Hydrogen plasma passivation was carried out in a radio fre- quency (rf) parallel-plate plasma reactor to passivate residual Si dangling bonds at the SiO 2 /poly-Si interface and in the poly-Si grain boundaries. SiO 2 /SiN x films acting as postmetal dielectrics were de- posited and etched for contact holes. Mo/Al/Mo metal layers were deposited and patterned to form the source and drain electrodes and finally complete the p-channel TFT fabrication. The gated PIN diode was also adopted to investigate the NBTI degradation in the poly-Si channel bulk simultaneously. The structure and manufacture processes of the gated PIN diode are similar to the one of the pro- posed p-channel TFT. However, there are two doping regions in the gated PIN diode, including p-side (p þ doping with the boron dose of 8  10 14 cm 2 ) and n-side regions (n  doping with the phosphorous dose of 1  10 13 cm 2 and n þ doping with a dose of 8  10 14 cm 2 ). When the gated PIN device was under NBTI stress, the negative gate bias sweep was applied to the gate electrode of the gated PIN diode, 0 V on the p-side region, and n-side floated. The gate bias stressing was relaxed periodically to explore device operation characteristics. The electrical operation conditions for device characterization are sche- matically shown in Fig. 1. The reverse generation current of the gated PIN diode was determined at V P ¼2.5 V, with n-side grounded and gate bias sweeping. Figure 1. Schematic cross-sectional views of the proposed gated PIN diode. The electrical connection to the gated poly-Si PIN diodes was set up at the junction reverse bias condition with gate bias sweeping. z E-mail: ptliu@mail.nctu.edu.tw Electrochemical and Solid-State Letters, 14 (5) H194-H196 (2011) 1099-0062/2011/14(5)/H194/3/$28.00 V C The Electrochemical Society H194 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 54.221.180.8 Downloaded on 2016-10-31 to IP