IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 9, SEPTEMBER 2011 3173 A Nondestructive Method for Accurately Extracting Substrate Parameters of Arbitrary Doping Profile in Nanoscale VLSI Yiorgos I. Bontzios, Michael G. Dimopoulos, Member, IEEE, and Alkis A. Hatzopoulos, Senior Member, IEEE Abstract—In this paper, a new approach is presented for deter- mining the substrate parameters of an arbitrary doping profile. It is general, technology independent, nonintrusive, and relies on simple direct-current measurements. A single measurement is required for uniform substrates, whereas two more measurements are needed for each additional layer in the multilayer case. Two different kernels are introduced for substrate resistance computa- tion. One features a closed-form analytical solution of the Laplace equations defining the problem under study. The other relies on a geometric formulation of the current streamlines in order to compute the substrate resistance. Both simulations and measure- ments are exploited in order to show the validity of the proposed scheme. For measurements, data from literature are utilized and also data from a fabricated test chip. The results demonstrate that the proposed method succeeds in computing the substrate parameters fast and with high accuracy. In uniform substrates, the error falls to zero, whereas, in epitaxial substrates, the average error is kept bellow 4%. Index Terms—Conductivity measurement, electric variables measurement, electromagnetic analysis, geometric modeling, in- tegrated circuit doping, resistance measurement, very large scale integration (VLSI). I. I NTRODUCTION I N THE deep submicrometer era, the feature size scales down, while at the same time, the chip’s complexity, speed, and clock frequencies increase. The influence of substrate noise coupling on the overall chip performance has taken an increasingly important role. Substrate noise coupling, if not carefully considered, may lead in violations of the spectral mask requirements, which, in most cases, results in a time consuming and expensive redesign process. Manuscript received November 4, 2010; revised February 13, 2011; accepted February 14, 2011. Date of publication April 5, 2011; date of current version August 10, 2011. This research is supported in part by Hellenic Funds and in part by the European Regional Development Fund under the Hellenic National Strategic Reference Framework (HNRF) 2007–2013 under Contract MICRO2- 47 of the Project “Next Generation Millimeter Wave Backhaul Radio” within the Program “Hellenic Technology Clusters in Microelectronics—Phase-2 Aid Measure.” The Associate Editor coordinating the review process for this paper was Dr. Subhas Mukhopadhyay. Y. I. Bontzios and A. A. Hatzopoulos are with the Department of Electri- cal and Computer Engineering, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece (e-mail: gmpontzi@auth.gr; alkis@eng.auth.gr). M. G. Dimopoulos is with the Department of Electronics, Alexander Tech- nological Educational Institute of Thessaloniki, 57400 Thessaloniki, Greece (e-mail: mdimop@ieee.org). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIM.2011.2124790 Several methods have been reported for the noise coupling prediction [1]–[6], all requiring the exact substrate doping profile for an accurate result. Since information about the doping profiles for a used technology node is generally missing (foundries do not disclose the relevant information), designers have great difficulty in checking (before tape-out) whether the designed circuit will suffer from substrate noise problems. Currently, accurate doping profile measurements are only possible by means of specialized techniques such as the atomic force microscopy (AFM) and particular the conductive AFM, tunneling AFM or scanning tunneling microscopy, scanning spreading resistance microscopy, and scanning capacitance mi- croscopy [7]–[9]. The major drawback of these techniques, apart from the necessary high-cost instrumentation is that they are destructive, i.e., a relatively large area of the chip is de- stroyed in order for the measuring probes to be inserted in the substrate. Nondestructive techniques have been also developed based on the measurement of the C–V characteristics of the p-n junction. However, these measurements may provide only the profile of a small area around the junction, which is of little use when global noise coupling is under consideration. Additionally, the doping profile is given only approximately by the conventional analysis of C–V measurements [10]. The aforementioned techniques provide information for the carrier concentration profiling (CCP) of the measured space area. Except for device study, e.g., to characterize the behavior of a metal–oxide–semiconductor (MOS) transistor, the accurate CCP is not necessary for the substrate noise prediction and computation in the system level. Instead, the resistivity value of the substrate is used for noise considerations in the design phase, which can be incorporated to Simulation Program with Integrated Circuit Emphasis-like simulators. Thus, the CCP must be first translated to a resistivity value before it can be used by simulators. In [11], the authors try to develop a rather com- plex methodology, which relies on a series of many different simulators, in order to avoid detailed information about doping. In [12], the resistivity is extracted by measurement data from the test structures. The substrate is stratified to a number of uni- form layers that are each described by two parameters, i.e., its height and its resistivity. An electromagnetic simulator is then used to match the measurement data to that of the simulator. Although sufficiently accurate, this method requires significant amount of time and a fair knowledge of electromagnetic (EM) simulations. The method proposed by Peterson et al. [13] is also based on the measurement data of the test structures, but it 0018-9456/$26.00 © 2011 IEEE