JOURNAL DE PHYSIQUE Colloque C4, supplbment au no9, Tome 49, septembre 1988 PHYSICAL BEHAVIOUR MODELLING OF VDMOS DEVICES J. PAREDES, J. FERNANDEZ, F. BERTA, S. HIDALGO, J. REBOLLO and J. MILLAN Centro Nacional de ~icroelectr&ica, CSIC-UAB , SP-08193 Bellaterra, Barcelona, Spain RBsumB - Mous proposons un modsle analytique pour expliquer le comportement physique des transistors VDhTOS quel que soit le niveau de courant. L'effect de quasi-saturation est pris en comate au travers de la saturation de la vitesse des porteurs B fort champ Blectrique. Des transistors VDMOS interdigitgs ont 6t6 realisgs et les simulations bidimensionelles effectueBs en vue de verifier le mod5le. Abstract - An analytical model is proposed in order to explain the physical behaviour of VDMOS devices at any DC current level. The quasi-saturation effect is included considering the carrier saturation velocity at high electric fields. Interdigitated VDXOS devices have been fabricated and 2D simulations have been carried out to check the model. 1 - INTRODUCTION The vertical DNOS transistor is one of the most usual drivers in power NOS ICs /I/. The linear region of its I-V characteristic has been modelled considering a surface accumulated layer, the JFET resistance between cells and a bulk epilayer resistance together with the active channel /2/. Moreover, in previous works /3, 4/ the current pinching was responsible for the quasi-saturation (q-s) effect or limitation in the current handling capability typical at high current levels. In contrast, 2D simulations /5/ have not shown current pinching between cells but, contrarily, there is a majority carrier excess in the JIET region, suggesting that q-s effect is due to carrier velocity saturation. The carrier excess was explained by means of a dipole similar to the one formed in a JFET channel under carrier velocity saturation conditions. However, none of the previous models has quantitatively explained these phenomena. This work is aimed to study the detailed physical behaviour of the VDMOS to avoid the tedious 2D CAD. Interdigitated VDMOS structures have been fabricated and 2D simulations /6/ have been carried out in order to check the proposed model. Due to the axial symmetry of the VDMOS structure (see fig I), current and electric field equations can be simplified to one-dimensional analysis: where n is the epilayer doping level and A(y) is the cross-section area of the current path. ~uitablgapproximations in the different regions of the epitaxy have been taken into account in order to obtain analytical solutions for the electric field distribution and for the majority carrier concentration; as shown in fig. 1, these regions are, namely: a) the surface accumulated layer induced by the gate effect of the MOS structure; b) the JFET region between cells and c) the drift region up to the drain contact. a) SUPERFICIAL REGION. The limits of this region are the Si-Si02 interface and the null electric field point inside the epilayer (yb), which is a consequence of the device bias; i.e., V and V are both positive while the source is grounded, so it must exist a point of G D Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:19884130