IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 4, APRIL 2008 1501 High-Bandwidth Multisampled Digitally Controlled DC–DC Converters Using Ripple Compensation Luca Corradini, Student Member, IEEE, Paolo Mattavelli, Member, IEEE, Elisabetta Tedeschi, Student Member, IEEE, and Daniele Trevisan, Student Member, IEEE Abstract—This paper investigates multisampled digitally con- trolled switched-mode power supplies with switching ripple com- pensation. In digital controllers for power converters, the main bandwidth limitations come from A/D conversion time, compu- tational delays, and small-signal delay of the digital pulsewidth modulator (DPWM). In hard-wired digital-controller technolo- gies, such as in dedicated digital IC and/or in field-programmable gate arrays (FPGAs), the calculation delays can be made negligi- ble with respect to the switching period; thus, when fast ADCs are used, the overall phase lag is dominated by the DPWM. The multisampling approach can strongly reduce the DPWM delay, thus breaking the bandwidth limitations of conventional single-sampled solutions. In this paper, the additional aliasing effects, which would require a filtering action, are avoided, exploit- ing the periodic nature of the switching ripple under steady-state conditions using a repetitive-based filtering action. Simulation and experimental results on a 1.2-V–10-A 500-kHz synchronous buck converter, where the digital control has been implemented in the FPGA, confirm the properties of the proposed solution. Index Terms—DC–DC converters, digital control, field- programmable gate array (FPGA), oversampling. I. I NTRODUCTION T HERE IS a growing interest in hard-wired digital control applied to high-frequency switched-mode power supplies (SMPS) both from scientific and industrial points of view [1]–[3], mainly with the aim of realizing dedicated integrated digital controllers (IDCs). In fact, IDCs offer several potential advantages compared with their analog counterparts, such as immunity to component variations and ability to implement sophisticated control schemes. On the other hand, the practical application of IDCs is still an open issue in the industrial com- munity, since one of the limiting factors of these technologies is the achievement of dynamic performances comparable to those of analog controllers in the presence of nonidealities, such as control delays and quantization effects, while keeping a simple control architecture with low silicon area require- Manuscript received June 30, 2006; revised September 13, 2007. L. Corradini is with the Department of Information Engineering, University of Padova, 35131 Padova, Italy (e-mail: luca.corradini@dei.unipd.it). P. Mattavelli and E. Tedeschi are with the Department of Technology and Management of Industrial Systems, University of Padova, 36100 Vicenza, Italy (e-mail: mattavelli@ieee.org; tedeschi@ieee.org). D. Trevisan is with the Power Electronic Laboratory, Department of Elec- trical, Mechanical and Management Engineering, University of Udine, 33100 Udine, Italy (e-mail: daniele.trevisan@uniud.it). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2008.917144 ments as imposed by the cost/complexity constraints in high- frequency SMPS in consumer, portable, computing, or net- working applications. With respect to the pulsewidth modulators (PWMs) com- monly employed in analog control solutions, sampled PWMs adopted in digital control schemes introduce an intrinsic delay time in the feedback loop [4]–[6], the entity of which limits the achievable system bandwidth. Such a delay represents the main source of bandwidth limitation when A/D conversion time and control processing time are negligible with respect to the switching period. This scenario is possible in the case of hard-wired digital controllers, such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits, where the control execution time can be reduced to a small fraction of the modulation period [1]–[3]. In conventional control architectures [1]–[3], [5], [6], a single sampling of the converter state variables is performed for each modulation period. In the case of fast A/D converters and dedicated hard-wired control logic, there is no additional cost in increasing the sampling frequency and the control- law frequency update with respect to the switching frequency. Thus, there is a recent deeper attention concerning the so-called multisampling techniques [7], [8] since they are very promising in reducing the PWM phase lag and ultimately breaking the bandwidth limitation. Besides these positive features, the multisampling technique has a major drawback since it injects high-frequency distur- bances (i.e., the voltage ripple) into the feedback loop. Once processed by the proportional-integral (PI) or PI-derivative (PID) regulators, these disturbances propagate through the feedback loop, causing malfunctions in the closed-loop system operation. For this reason, high-frequency ripple cancellation is required. The most straightforward approach is the antialiasing filter which, however, reduces the phase margin and the possible advantages of the multisampling technique. This paper investigates a ripple-elimination technique which does not waste the phase boost achieved through the multi- sampling approach. The proposed solution exploits the periodic nature of the high-frequency disturbances under analysis and adopts a repetitive-ripple-estimation approach to subtract the noise from the sampled error signal. The repetitive control solution, being a feedback technique, needs no preliminary knowledge of converter parameters. This paper is organized as follows. Section II describes the small-signal modeling and the discrete-time representation of the multisampled digital control. Section III analyzes the ripple- removal algorithm, and Section IV presents some simulation 0278-0046/$25.00 © 2008 IEEE