14 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 1, JANUARY 2006 A Three Charge-States Model for Silicon Nanocrystals Nonvolatile Memories Christophe Busseret, Stéphane Ferraton, Laurent Montès, and Jacques Zimmermann Abstract—In the field of nonvolatile memories, substantial improvement of reliability is obtained by replacing the contin- uous polysilicon floating gate by a planar distribution of silicon nanocrystals, each acting as a storage node. The test devices in the present paper are MOS capacitors containing a two-dimensional layer of nanocrystals located 2.5 nm away from the oxide/sub- strate interface, inside the SiO . This work presents various measurements of the charge current versus either bias voltage or time. On the other side, the charge and discharge dynamics of the nanocrystals had already been described by De Salvo using a model borrowed from the conventional floating-gate memory. We show this approach to be not completely suitable to explain the experimental observations. Thus, we describe and apply a so-called granular model, based on a mono-electronic principle limited by Coulomb blockade, in which electrons interact with the nanocrystals one by one. Omitting the reality of such a one-by-one principle may involve important mistakes in the interpretation of phenomena. Index Terms—Charge dynamics, modeling, nonvolatile single- electron memory, silicon nanocrystals (Si-nc). I. INTRODUCTION T HE never-ending downscaling of devices involves new challenges at each next generation. New technological processes, characterization techniques, devices architectures and simulators are continuously proposed in order to overcome the next barriers. Nonvolatile memories (NVMs) are subject to the same law of progress. Floating-gate memories could not be reduced further without changing some important parts of their architecture. As a matter of facts, quantum effects involves tunnel current leaking through oxides not previously leaky. Retention performance breaks down when using very thin oxides below 3 nm since everybody know that thick ox- ides do not allow efficient reduction of the gate length of the MOS control transistors. Therefore, alternative architectures have been proposed in order to overcome this difficulty and keep within the International Technology Roadmap for Semi- conductors (ITRS). As a result, the continuous floating-gate layer has been replaced by two-dimensional (2-D) layers of silicon nanocrystals (Si-nc) [1]–[3]. The charge carriers are stored inside these Si-ncs inducing a threshold voltage shift in analogy with conventional NVMs. The real advantage of this Manuscript received April 11, 2005; revised September 20, 2005. This work was supported in part by the Région Rhône-Alpes. The review of this paper was arranged by Editor R. Shrivastava. C. Busseret is with the Laboratoire de Physique de la Matière, INSA-Lyon, Villeurbanne, France (e-mail: christophe.busseret@insa-lyon.fr). S. Ferraton, L. Montès, and J. Zimmerman are with the Institut de Microélec- tronique, Electromagnétisme et Photonique (IMEP), UMR CNRS-INPG-UJF Grenoble 38016, France (e-mail: christophe.busseret@insa-lyon.fr). Digital Object Identifier 10.1109/TED.2005.860630 Fig. 1. Cross sectional view of a MOS capacitor containing a two-dimensional layer of Si-ncs acting as the floating-gate. Bias is applied to the top contact and the current is measured on the bulk and the guard ring connected together. This guard ring feeds the inversion layer with electrons. new design is that a leak in the oxide layer will discharge only one Si-nc, all the others remaining operational. The charging state of the memory cell would be preserved thanks to the latter. The reliability of this new kind of memory is believed to be substantially improved due to the discrete nature of the floating-gate. Moreover, read/write process at very moderate voltage is possible as compared with standard NVM. Low-pres- sure chemical vapor deposition (LPCVD) techniques are used to grow up two-dimensional Si-nc layers compatible with VLSI technologies. In general though, large dispersions in size of the Si-nc are observed. This dispersion is rarely taken into account in electrical simulators. Moreover, the models proposed in the literature are rather seldom. At present, the most popular model is based on a continuous floating-gate representation [4] borrowed from conventional floating-gate memories [5]. We will show the advantages and drawbacks of this description. Because this model is unable to accurately fit experimental measurements, we will propose a better approach. This new approach will take into account the granularity of the charge stored in the Si-ncs. Actually, these can only be filled up by electrons via a one-by-one process. Then we will be able to take into account the Si-nc size distribution and to correctly describe the behavior of devices having a large population of Si-nc, as well. II. EXPERIMENTAL The devices are MOS capacitors as simplified test structures of NVMs. A schematic cross section is shown in Fig. 1. The 2.5-nm tunneling insulating layer was prepared by thermal growth of thin SiO on p-doped Si(100) substrate. The Si-ncs were self-assembled in an LPCVD system. Deposition was 0018-9383/$20.00 © 2005 IEEE