2362 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011 Impact of Ge Content and Recess Depth on the Leakage Current in Strained Si 1−x Ge x /Si Heterojunctions Abraham Luque Rodríguez, Mireia Bargallo Gonzalez, Geert Eneman, Cor Claeys, Fellow, IEEE, Daisuke Kobayashi, Member, IEEE, Eddy Simoen, and Juan A. Jiménez Tejada, Member, IEEE Abstract—A study of the impact of the Ge content and the recess depth on the leakage current of strained Si 1-x Ge x /Si p + n heterojunctions is presented. A rise in the current, when the Ge content increases and/or the recess depth decreases, is experimentally observed. An analysis of the physical variables involved in the leakage current at low electric fields is carried out. The Shockley–Read–Hall lifetime is identified as the variable that affects the leakage current the most. Changes in the lifetimes are correlated to changes in the Ge content and the recess depth (Si 1-x Ge x thickness) by means of modifications of the stress levels. An expression that directly relates the values of the lifetimes with the germanium content is proposed. Index Terms—Leakage current, simulation of electronic devices, Si/SiGe heterojunctions, strain engineering. I. I NTRODUCTION T HE PRESENCE of heterojunctions in current semicon- ductor devices is quite common since the implementation of different materials is required to improve their perfor- mance in line with the International Technology Roadmap for Manuscript received February 26, 2011; revised April 12, 2011; accepted April 19, 2011. Date of publication May 23, 2011; date of current version July 22, 2011. This work was supported in part by the Ministerio de Educación y Ciencia and in part by the Fonds Européen de Développement Régional within the framework of Research Project TEC2010-16211. The review of this paper was arranged by Editor J. D. Cressler. A. Luque Rodríguez is with the Interuniversity Microelectronics Center, B-3001 Leuven, Belgium, on leave from the Departamento de Electrónica y Tecnología de los Computadores, Facultad de Ciencias, Universidad de Granada, 18071 Granada, Spain (e-mail: abrahamluque@ugr.es). M. Bargallo Gonzalez and C. Claeys are with the Interuniversity Micro- electronics Center, B-3001 Leuven, Belgium, and also with the Department of Electrical Engineering (ESAT)–Integrated System, Katholieke Universiteit Leuven, B-3001 Leuven, Belgium (e-mail: barga@imec.be; claeys@imec.be). G. Eneman is with the Interuniversity Microelectronics Center, B-3001 Leuven, Belgium, also with the Department of Electrical Engineering (ESAT)–Integrated System, Katholieke Universiteit Leuven, B-3001 Leuven, Belgium, and with the Fonds Wetenschappelijk Onderzoek–Vlaanderen, B-1000 Brussels, Belgium (e-mail: enemang@imec.be). D. Kobayashi is with the Interuniversity Microelectronics Center, B-3001 Leuven, Belgium, and also with the Department of Electrical Engineering (ESAT)–Integrated System, Katholieke Universiteit Leuven, B-3001 Leuven, Belgium, on leave from the Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara 252-5210, Japan (e-mail: d.kobayashi@isas.jaxa.jp). E. Simoen is with the Interuniversity Microelectronics Center, B-3001 Leuven, Belgium (e-mail: simoen@imec.be). J. A. Jiménez Tejada is with the Departamento de Electrónica y Tecnología de los Computadores, Facultad de Ciencias, Universidad de Granada, 18071 Granada, Spain (e-mail: tejada@ugr.es). Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2148723 Fig. 1. (a) Structure of a pMOSFET with a stressed channel. (b) Detail of an isolated heterojunction and the two components of the current in reverse- bias operation: Areal current density J A and peripheral current density J P . (c) Doping profile in the n-well Si substrate prior to the etching and after two kinds of implantations, i.e., deep phosphorous and arsenic implantations and shallow halo arsenic implantation. (Gray region) Part of the substrate that is subsequently etched out and refilled with a SiGe alloy layer. Semiconductors. That is the case for strained-silicon (ǫ-Si) p-channel metal–oxide–semiconductor field-effect transistors (pMOSFETs) [1], where an enhancement factor of the hole mobility over bulk Si of ∼2 is observed [2] and even greater factors are expected in optimized heterostructures [3]. This improvement is induced by the compressive uniaxial strain in the silicon, resulting from the growth of embedded Si 1−x Ge x (e-SiGe) in the source/drain (S/D) contacts [see Fig. 1(a)] [4]. In spite of the achievements on drive current/performance improvement, there are some undesired effects, such as an increased leakage current through the substrate in the OFF-state [5]. The S/D doping plays an important role in the device perfor- mance. Two types of doping techniques have been considered in the formation of the S/D junctions in complementary MOS (CMOS) technology. One is the in situ boron doping during the growth of the e-SiGe S/D, and the other is the boron implan- tation after the creation of an undoped e-SiGe contact layer. 0018-9383/$26.00 © 2011 IEEE