Cost Functions for the Design of Dynamically Reconfigurable Processor Architectures Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel University of Tuebingen Wilhelm-Schickard-Institute, Computer Engineering Sand 14, 72076 Tuebingen, Germany crc@informatik.uni-tuebingen.de Abstract— There are a growing number of recon- figurable architectures that combine the advantages of a hardwired implementation (performance, power con- sumption) with the advantages of a software solution (flexibility, time to market). Today, there are devices on the market that can be dynamically reconfigured at run-time within one clock cycle. But the benefits of these architectures can only be utilized if applications can be mapped efficiently. In this paper we describe a design approach for reconfigurable architectures that takes into account the three aspects architecture, com- piler, and applications. To realize the proposed design flow we developed a synthesizable architecture model. From this model we obtain estimations for speed, area, and power that are used to provide the compiler with the necessary timing information and to optimize the architecture. I. Introduction A lot of research in the area of reconfigurable computing systems is focused on the re-use of devices like FPGAs for different applications. But compared to this, newly devel- oped devices provide much more advantages. They allow re-using the functional elements of a device for different op- erations within a single application. This is accomplished by extremely fast reconfiguration (in less than a clock cy- cle) during run-time. For these devices, frequent reconfigu- ration is part of the regular execution. The reconfiguration keeping pace with the execution yields an additional degree of freedom that constitutes a new principle of reconfigura- tion. We name this new principle processor-like reconfigu- ration. By means of reconfigurable data paths, processor- like reconfiguration allows it to instantiate and to execute within one clock cycle exactly that part of a circuit that is needed in this cycle. Although for each of the new archi- tectures distinct advantages have been presented, by today none of them was able to gain significant market shares in industry. From the technical point of view, our practical ex- periences have shown the following reasons for this: 1) the design tool to map applications onto the architecture (the compiler) is developed after the architecture was defined, 2) the language provided to users for application design is not appropriate, or 3) suitable applications are sought after the architecture was developed. This demonstrates that a good architecture by itself does not provide a good solution. In fact, the benefits of reconfigurability can only be exploited if applications can be mapped efficiently onto the available architectures. In this context we focus on two problems that need to be solved. The first problem is that different applications need different architectures. This is due to the fact that the area of Reconfigurable Computing mostly stresses the use of coarse grained architectures [1]. Accordingly, the commer- cial architectures are also coarse grained. For such archi- tectures various properties (e.g. the data path width) are fixed at fabrication time of the device. This means that only applications that fit these properties can be mapped onto these architectures without wasting a significant amount of resources. The second problem that we focus on is the avail- ability of a compiler to map applications onto the architec- ture. Such a compiler must be able to automatically map applications that are described on high levels of abstrac- tion, i.e., the algorithmic and system level. In our opinion application design at the register-transfer (RT) level is not an option. In ASIC/FPGA design the implementation at the RT level already leads to a productivity gap between the number of gates provided by modern process technolo- gies and the number of gates that can be implemented by application design teams. Reconfiguration yields a further degree of freedom that increases design complexity even more. Our approach to solve these problems is a design en- vironment for reconfigurable architectures that takes into account the three aspects architecture, compiler, and appli- cations. The environment supports an iterative flow where the architecture and the compiler are refined concurrently. This refinement is driven by the analysis of applications from a given problem domain (e.g. encryption or graphical systems). The result of the iterative flow is an architec- ture together with a compiler which are optimized for the specified problem domain. As the starting point for the architecture we have defined the CRC model depicted in Fig. 1. The CRC model is a very general model for processor-like reconfigurable archi- tectures that can be configured with a variety of parameters during the refinement process. This configuration and the reconfiguration of the architecture during run-time account for the name CRC (Configurable Reconfigurable Core). It is oriented towards commercially available architectures to