IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 4, APRIL 2008 997 Gate Oxide Wear-Out and Breakdown Effects on the Performance of Analog and Digital Circuits Raul Fernández, Member, IEEE, J. Martín-Martínez, R. Rodríguez, Montserrat Nafría, Senior Member, IEEE, and Xavier H. Aymerich, Member, IEEE Abstract—To investigate the impact of gate oxide degra- dation and breakdown (BD) on complimentary metal–oxide– semiconductor circuit functionality, an accurate description of the electrical characteristics of the stressed devices, which can be included in circuit simulators, is needed. In this paper, a descrip- tion of the stressed device performance that considers, on the one hand, the variation of the channel current and, on the other, the increase in the gate current due to the oxide degradation and BD is presented, which is able to account for different levels of ox- ide damage. The parameters extracted from device experimental data have been introduced in a circuit simulator to evaluate the effect of the oxide degradation and BD on simple analog (current mirror) and digital [reset set (RS) latches] circuits. The impact of the increase in the gate leakage current and the variation of the conduction along the metal–oxide–semiconductor field-effect transistor channel due to the oxide degradation on the circuit performances has been separately analyzed. Index Terms—Complimentary metal–oxide–semiconductor (CMOS), dielectric breakdown (BD), hard BD (HBD), oxide reliability. I. INTRODUCTION G ATE oxide thickness and metal–oxide–semiconductor field-effect transistor (MOSFET) channel dimensions have rapidly decreased in the last years as a consequence of the continuous scaling of devices [1], leading to the appearance of several failure mechanisms, which limit the integrated circuit reliability. In the case of the gate oxide, the dielectric break- down (BD), i.e., the loss of its dielectric properties, is one of the most important. However, previous works seem to indicate that the oxide BD effect is overestimated and that devices and cir- cuits can still work after an important level of oxide degradation [2]–[4]. Therefore, the analysis of the impact of dielectric BD (and of its prior degradation) on metal–oxide–semiconductor devices and circuit functionality is critical for the evaluation of present complimentary metal–oxide–semiconductor reliability. In this direction, to advance this study, the development of models for broken-down devices that can be included in circuit simulators is needed [5]. Customarily, the effect of BD on Manuscript received November 26, 2007. This work was supported in part by the Ministry of Education and Science of Spain under Grant TEC2004- 00798/MIC, by the DURSI of the Generalitat de Catalunya under Grant 2005SGR-00061, and by the European Commission (Marie Curie Actions under the APROTHIN Project). The review of this paper was arranged by Editor J. Suehle. The authors are with the Departament d’Enginyeria Electrònica, Univer- sitat Autònoma de Barcelona, 08193 Barcelona, Spain (e-mail: rfernan@eel. upc.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2008.917334 device performance has been studied through the variation of some device parameters (off current, threshold voltage, transconductance, etc.) [6]–[8], but less attention has been paid to the modification of the complete output characteristics of the device (I D –V DS ). In addition, equivalent electrical circuits for field-effect transistors broken down at different positions of the channel have been presented, which can be included in Simulation Program with Integrated Circuit Emphasis (SPICE) simulators [2], [9]. In these cases, different equivalent circuits are needed, depending on the BD hardness and BD position along the channel, but the possible effects of BD on other device parameters [6], [7] are not considered. An alternative is the description of the broken-down MOSFET using models such as the Berkeley Short-channel IGFET Model (BSIM), whose parameters are extracted after the oxide BD [10]. However, when this is done, the gate BD current is not usually considered [11]. Independent of the approach, BD is the main focus, but much less attention has been paid to the effects of the degradation prior to the device BD [12], which can have a large impact on the analog circuit performance. In this paper, a unified approach for the description of the electrical characteristics of worn-out (before BD) and broken- down MOSFETs is presented, which can be easily introduced in circuit simulators and simultaneously considers the increase in the gate current and the modification of the conduction through the channel due to the oxide degradation. In this approach, the I –V curves of the device in all the operational regions are described using an equivalent circuit for the post- BD gate current and the BSIM4 SPICE model to account for the variation of the current along the channel. The data obtained from n-channel MOSFETs (nMOSFETs) of several geometries that have suffered different levels of oxide degradation and/or BD at different locations along the channel have been correctly described using this approach. They have been introduced in a circuit simulator to evaluate the impact of degradation and BD on the functionality of simple analog and digital circuits. II. EXPERIMENT nMOSFETs of 1.5-V bulk technology with SiO 2 or SiON as gate dielectric have been studied. For SiO 2 devices (tox = 2.2 nm), two different aspect ratios W/L = 10 μm/10 μm and W/L = 10 μm/0.175 μm have been considered. SiON devices (1.6-nm equivalent oxide thickness) were much narrower, with a W/L ratio of 0.35 μm/0.13 μm. Constant voltage stresses (3.7 and 3 V for the SiO 2 and SiON samples, respectively) were applied to the gate, with the other terminals grounded to 0018-9383/$25.00 © 2008 IEEE