Efficient Simulation-based Debugging of Reversible Logic Stefan Frehse Robert Wille Rolf Drechsler Institute for Computer Science Bibliothekstraße 1 28359 Bremen, Germany {sfrehse,rwille,drechsle}@informatik.uni-bremen.de Abstract—Reversible logic has become an active research area due to its various applications in emerging technologies, like quantum computing, low power design, optical computing, DNA computing, or nanotechnologies. As a result, complex reversible circuits containing thousands of gates can be efficiently synthesized, today. However, this also increases the probability of design errors. While for the detection of errors already a couple of simulation-based or formal verification techniques have been proposed for reversible logic. Research in the domain of debugging is still at the beginning. In this paper, we present an automatic debugging approach for reversible logic which is based on simulation. We show that a particular error in a gate always requires a counterexample leading to a concrete gate input pattern. By simulating all counterexamples and checking for these input patterns, irrelevant gates (i.e. gates that do not contain an error) can be excluded. Experiments show, that applying the proposed approach leads to speed-ups of up to five orders of magnitude. Furthermore, the number of error candidates can be reduced in comparison to previous work. I. I NTRODUCTION While nowadays circuit technologies more and more start to suffer from the increasing miniaturization and the exponential growth of the number of transistors, reversible logic [1], [2], [3] offers a promising alternative. Here, functions are realized that map each input pattern to a unique output pattern (i.e. bijections are realized). The resulting reversibility enables applications particularly in areas like e.g. quantum computation [4] or low power design [5], but also in optical computing [6], DNA computing [2], and nanotechnologies [7]. However, in contrast to traditional CMOS circuits, reversible logic is subject to some important restrictions. For example, fanout and feedback are not allowed [4]. Therefore, a complete new gate library and circuit structure was introduced [3]. More precisely, reversible circuits are cascades of reversible gates. This also affects the design flow which has to be reorganized and where single steps need considerable modifications to support reversible logic. In the last years, researchers particularly focused on synthe- sis (see e.g. [8], [9], [10], [11], [12]). While at the beginning, synthesis of reversible logic was only possible for very small functions (i.e. for functions with up to 30 variables), in the meanwhile approaches have been introduced that handle 100 and more variables [12]. As a consequence, also the resulting reversible circuits increased in their size and complexity, so that the focus more and more moves from synthesis also to further steps in the design flow such as simulation [13], [14], optimization [15], [16], testing [17], [18], [19], and formal verification [20], [21], [22]. In particular, automatic methods for checking the correctness become more important as with increasing circuit sizes this cannot be manually ensured any longer. However, while methods for simulation, testing, or veri- fication can only be used to detect the existence of errors, they provide no support to locate the source of an error. Thus, recently also a first approach for automatic debugging of errors has been proposed [23]. Here, given an erroneous circuit and a set of counterexamples, a set of gates (so called error candidates) is returned, whose replacements with other gates fix the counterexamples, The debugging problem has been thereby encoded as an instance of Boolean satisfiability (inspired by circuit debugging for non-reversible circuits [24]) and solved by an efficient SAT solver [25]. In this paper, we introduce an alternative debugging ap- proach that relies on the simulation of counterexamples. An observation is thereby exploited stating that a particular error in a gate always requires a counterexample leading to a concrete gate input pattern. Thus, by simulating all available counterexamples and checking for these input patterns, irrel- evant gates (i.e. gates that definitely do not contain an error) can be excluded. This leads to the following advantages: • The number of gates which have to be further considered is significantly reduced. Sometimes, already this leads to a single error candidate, i.e, the concrete error location. • Due to the simulation-based nature of the approach this reduction can be achieved in very low run-time. • The proposed approach can be additionally used as pre- processor for further debugging methods. More precisely, in a first step the number of gates to be considered is significantly reduced by the proposed simulation-based approach. If then still a notable number of error can- didates remains, this set can be further refined e.g. by the approach from [23]. In doing so, for the first time debugging becomes feasible even for circuits containing hundreds of thousands of gates. Our experiments confirm these advantages as speed-ups of up to five orders of magnitude are achieved. Furthermore, the number of error candidates can be significantly reduced in many cases in comparison to previous presented SAT-based approach [23]. 40th IEEE International Symposium on Multiple-Valued Logic 0195-623X/10 $26.00 © 2010 IEEE DOI 10.1109/ISMVL.2010.37 156 40th IEEE International Symposium on Multiple-Valued Logic 0195-623X/10 $26.00 © 2010 IEEE DOI 10.1109/ISMVL.2010.37 156