IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 1 | July 2016 ISSN (online): 2349-784X All rights reserved by www.ijste.org 198 Reduction of Power Dissipation in SRAM using Adiabatic Logic Sridhar S V Mahesh B Neelagar PG Student Assistant Professor Department of VLSI Design & Embedded Systems Department of VLSI Design & Embedded Systems VTU PG Center, Belagavi VTU PG Center, Belagavi Abstract Static RAM is a temporary storage memory used in cache memory. It is a fast access memory and it is prone to high power dissipation. Adiabatic logic technique is one among the many low power techniques in VLSI design to reduce power dissipation. Adiabatic logic is implemented to SRAM to reduce power dissipation. Among the various adiabatic techniques, Split Level Charge Recovery Logic (SCRL) is used to reduce power dissipation in SRAM. Adiabatic logic is implemented for conventional 5T SRAM in this paper. The operation of adiabatic logic implemented SRAM is similar to the operation of conventional SRAM. Clocks have been used instead of DC supply and transmission gates are used. Size of the SRAM becomes large but it is overcome by reduction in the power dissipation. Simulation is done in 45nm technology using Cadence. Keywords: 5T SRAM, Adiabatic Logic, Cache Memory, SCRL, Transmission Gates ________________________________________________________________________________________________________ I. INTRODUCTION SRAM is static memory which holds information cross coupled inverter until power is being applied to cross coupled inverter. It does not need periodic refreshing like DRAM and it is faster and expensive than DRAM and consumes less power than DRAM. To reduce the power dissipation, the circuit designer can minimize the switching events, decrease the node capacitance, or he can minimize the voltage swing, or he can apply a combination of these methods. Adiabatic logic circuits offers the possibility of reducing energy dissipation during the switching events and the possibility of recycling, reusing some of the energy drawn from the supply. Adiabatic logic reuses the energy stored in the load capacitors instead of discharging the load capacitors to the ground like conventional way and wasting that energy. II. CONVENTIONAL 5T SRAM Fig 1 shows schematic conventional 5T SRAM. WL denotes Word Line, BL denotes Bit Line, D denotes data stored in SRAM cell and Dbar denotes complement of D. WL is made high to turn on the access transistor n1. DC supply voltage VDD is applied to cross coupled inverters. For storing 1, BL is made high and 1 is passed through access transistor to D node. The value at D serves as input to second inverter and this inverter outputs the complement value of D. The value at Dbar serves as input to first inverter. The output of first inverter will be the complement of value at Dbar. That output value will be the value which was passed through access transistor. Hence at any time, the value at D node will the value which was sent to store in SRAM through access transistor n1. The same operation holds good for storing 0 into the SRAM cell. Fig. 1: Conventional 5T SRAM III. PROPOSED 5T SRAM Fig 2 shows circuit of adiabatic 5T SRAM. Clock supply is used for inverters instead of DC supply. The charging and discharging of gate capacitor is slowed down by using a clock with suitable rise and fall times. Hence the time period T, which is charging period, increases. As per the energy dissipation formula EDISS = C VDD 2 (RC/T), if charging time increases, energy dissipation decreases. Fig 3 shows the trapezoidal clocks used in the proposed 5T SRAM cell.