A zyxw Flexible Approach to the Design of Complex Embedded Systems Jost M. Moya, Francisco Moya, Juan Carlos L6pez University of Castilla-La Mancha Paseo de la Universidad, zyxwv 4. 13071 Ciudad Real, Spain {jmmoya,fmoya,jclopez}@inf-cr.uclm. es zyxw Abxrrucr- This article describes a new approach to hardware- software codesign for complex embedded systems, using high-level programming languages, such as C, C++, Java, or Ada. Unlike pre- vious approaches, we do not distribute parls of the behavior between the different subsystems. We map the entire behavior onto the whole system, and the partition is made implicitly during the synthesis pro- cess. We divide the system specification into behavior, architecture and design criteria, to maximize reuse opportunities and to increase the flexibility zyxwvutsrqpo of the design environment. I. INTRODUCTION Nowadays, the embedded systems community tends to use standard general-purpose microprocessors with little or no specific hardware. This trend is consistent with the in- creased adoption of COTS component-based methodolo- gies to reduce development time. Many factors contribute to this situation: 1) A vast ma- jority of the embedded systems designers are not familiar with state-of-the-art ASIC design tools. 2) There are lots of tightly integrated, well tested tool chains for embedded software development but almost none of the EDA tools have been integrated into these tool chains yet. 3) Consid- erably less training is needed to effectively use software de- velopment environments compared to their hardware coun- terparts. 4) And software development enjoys shorter itera- tions during the development process. Nevertheless the current approach, compared to a judi- cious combination of ASICs and off-the-shelf micropro- cessors, leads to oversized microprocessors, lower perfor- mance and potentially higher production costs. Nowadays flexibility is not an issue given the availability of many re- configurable devices. The introduction of application-specifichardware during the design of an embedded system brings a lot of problems: Methodologies and tools used for hardware and software development are very different from each other. They use different specification languages and there are very few en- gineers with enough expertise in both, hardware and soft- ware development. Development cost is usually much higher. Partitioning the functionality between hardware and soft- ware components must be done very early in the design pro- This work is funded by CICYT project TIC2000-0583-CO2 cess, which usually leads to suboptimal results. There are not enough criteria during early stages of the design cycle. Given there is not an unified methodology, hardware de- velopment and software development are carried out inde- pendently of each other. This precludes potential optimiza- tions and makes it harder to integrate both parts. Current technologies for designing hardware-software systems do not scale well. When we face large prob- lems manual partition becomes impractical, and automatic partitioning (based on the iterative evaluation of a signif- icant amount of alternatives) becomes unacceptably slow because the design space grows exponentially with the size of the problem. In this paper we present a new methodology to hardware- software codesign specially designed to overcome these limitations of current approaches to the design of complex embedded systems. 11. RELATED WORK During the last decade, the research community has shown a strong interest in the unification of hardware and software specifications to simplify the design of complex hardware-software systems. High-level programming lan- guages are common in large-scale system design and de- bugging, and they are now being considered for the whole design process. Recent works on the hardware implemen- tation of pointers [l] contribute to support the idea of a gen- eral purpose programming language as a system-level spec- ification language. Some advances in this area come from adding support of a formal model of computation to a programming lan- guage. POLIS [2] uses the Esterel language to implement communicatingjnite state machines. A textual netlist aux- iliary language is used to specify the interconnection be- tween the FSMs. The underlying formal model, globally asynchronous and locally synchronous, is called codesign finire stare machines (CFSMs). In [3], the synchronous re- active semantics is implemented as a Java class library. Other research groups have developed new specification languages based on a certain model of computation, and making no attempt to be compatible with any other exist- ing language. V++ [4] is based on the synchronous model, 0-7803-6741-3/901/$10.00 zyxwvutsr 0 2001 IEEE 237