Using PARBIT to Implement Partial Run-Time Reconfigurable Systems EdsonL.Horta 1 ,JohnW.Lockwood 2 ,andS´ ergio T. Kofuji 1 1 Department of Electronic Engineering, Laboratory of Integrated Systems, Escola Polit´ ecnica da Universidade de S˜ao Paulo, Av. Prof. Luciano Gualberto, trav. 3, 158. CEP 05508-900 - S˜ao Paulo, SP, Brazil, edson-horta@ieee.org, 2 Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO 63130, lockwood@arl.wustl.edu, http://www.arl.wustl.edu/arl/projects/fpx/parbit Abstract. Field Programmable Gate Arrays (FPGAs) can be used to implement partial run-time reconfigurable (RTR) systems. A tool called PARBIT has been developed that transforms FPGA configuration bit- streams into partial bitstreams. With this tool it is possible to define a partial reconfigurable area inside the FPGA and download it into a specified region of the FPGA device. This paper presents PARBIT, the methodology used to design the partial RTR system, and three applica- tion examples. 1 Introduction Field Programmable Gate Arrays (FPGAs) enable hardware circuits to be re- configured an unlimited number of times. The implementation of a system that uses reconfigurability can be done in two ways: Compile-Time and Run-Time Reconfiguration [1]. For Compile-Time Reconfiguration (CTR) the FPGA does not change configuration during the application lifetime. Each application has specific functions that are loaded when the FPGA is started. Some examples of CTR systems are SPLASH [2] and PAM [3]. For Run-Time Reconfiguration (RTR),theFPGAchangesconfigurationwhileitisoperating.RTRcanbetotal (all the device is reprogrammed) or partial (only part of the device is repro- grammed). Existing platforms have focused on reconfiguration of entire FPGA devices [4] [5] [6]. Some recent work has considered partial reconfiguration [7] [8]. Partial reconfiguration is a difficult task, especially in systems that require both partial reprogramming and run-time reconfiguration. In order to partially reconfigure a FPGA, it is necessary to isolate an specific area inside the FPGA anddownloadtheconfigurationbitsrelatedtothatarea.AtoolcalledPARBIT (PARtial BItfile Transformer) [9] has been developed to easily transform and restructure bitstreams to implement dynamically loadable hardware modules. M. Glesner, P. Zipf, and M. Renovell (Eds.): FPL 2002, LNCS 2438, pp. 182–191, 2002. c  Springer-Verlag Berlin Heidelberg 2002