2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link Y. Katayama, C. Haymes * , D. Nakano, T. Beukema * , B. Floyd * , S. Reynolds * , U. Pfeiffer * , B. Gaucher * , and K. Schleupen * IBM Tokyo Research Laboratory * IBM T. J. Watson Research Center E-mail: {yasunaok, dnakano}@japan.ibm.com, {haymes, troyb, brianfl, skreyn, ullrich, bgaucher, kais}@us.ibm.com Abstract— We report a proof-of-concept demonstration of 2- Gbps uncompressed HDTV transmission using a 60-GHz SiGe radio chipset. We took a single-carrier approach with a usual DQPSK modulation scheme, assuming an LOS environment, and implemented the system with FPGAs. At the same time, in order to take care of more frequent sync/burst errors in high-data-rate single-carrier approaches, we equipped the baseband with effi- cient random/packet error recovery and symbol-timing recovery with an effective interpolation method. As a result, a clear and crisp image was obtained in the end-to-end transmission. I. I NTRODUCTION Millimeter wave technology is expected to bring secure wireless connectivity at leading-edge wireline speed. It can open up new applications in home electronics, in the office, and for infrastructure without interfering existing microwave wireless bands. In particular, the band around 60 GHz can be used without a license in many countries including the United States and Japan, and standardization activity is going on at IEEE 802.15.3c. So far, most known system-level implementations in and above 60-GHz band were with GaAs (or other III-V com- pounds) RF components. Our recent achievements with a 60- GHz SiGe RF chipset [1], [2] open up new silicon-based possi- bilities of using the millimeter wave technology for consumer and office applications at low cost, comparable to today’s wireless LAN technology. With appropriate CMOS digital baseband technology, ultrahigh-speed wireless connectivity can be realized ubiquitously. In this paper, we report on a system-level demonstration of millimeter wave technology using our SiGe radio chipset. We took a single carrier approach with a usual DQPSK modulation scheme and implemented the system in FPGAs to build up the system quickly at low risk. At the same time, to take care of more frequent sync/burst errors in high-data-rate single- carrier approaches, the baseband is equipped with efficient ran- dom/packet recovery scheme and digital sampling technique with effective interpolation method. We believe that the present demo can lead to affordable but ultra-high-speed point-to-point links with silicon-based 60GHz RF modules and also can be a stepping stone toward sophisticated modulation and coding schemes for more complicated network connections. II. SYSTEM DESIGN CHALLENGES The primary purpose of the present demo system is to show that our silicon-based RF modules work with multiple- Gbps digital baseband technology. We chose to build a demo system using FPGA-based infrastructure for a short turnaround time. The FPGA-based system also allows us to test various coding schemes without redesigning the baseband chip. We generally assumed an LOS environment exists for our demo, for a simpler modulation scheme like single-carrier DQPSK. Perfect NLOS (Non Line Of Sight) transmission in millimeter frequencies at a data rate of multiple Gbps and above will require further consideration in baseband signal processing. However, the single carrier approach will make clock and data recovery more difficult. Since a single carrier needs to transmit a multi-Gbps data stream without splitting it into multiple subcarriers, typical channel delay spread is much larger than the symbol period. Even though the use of CDR (Clock Data Recovery) to recover bit timing is well-established and will lead to low-cost and low-power implementations for relatively clean channel environment, the maximum data rate for a given BW is often reduced to the half, since we cannot separate the I and Q channels. In addition, the CDR approach will not allow us to consider potential extensions for more advanced and robust baseband signal processing techniques for nonnegligible multi-path effects, etc. On the other hand, even though the use of a digital sampling approach with high-speed ADC will allow us to adopt more advanced signal processing techniques, the receiver side timing recovery will become more difficult, causing more frequent sync/burst errors. Unfortunately, system-level techniques such as ARQ does not work with a unidirectional link configuration. Even if the control line for handshaking is available, buffering and latency overhead can often make the ARQ approach inefficient. After comparing pros and cons of the above two approaches, we decided to take the latter approach for the present demo primarily because the maximum data rate can become twice. Instead of transmitting 1 Gbps, we can transmit 2 Gbps. Since we cannot rely on the CDR for timing recovery, syn- chronization patterns needs to be distributed in the video stream to adjust for the frequency differences between the transmitter and receiver as well as to recover from sync/burst errors quickly. Efficient packet recovery scheme is needed, in addition to random error correction capability, in order to ensure sufficient robustness against sync/burst errors. At the same time a high code rate is needed to avoid large parity overhead. Also, even though the advantages of using FPGAs are clear, they often limit the complexity and throughput of 1-4244-0667-6/07/$25.00 © 2007 IEEE 12