IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 6, JUNE 2015 1453 Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability Alﬁo Dario Grasso, Member, IEEE, Davide Marano, Gaetano Palumbo, Fellow, IEEE, and Salvatore Pennisi, Senior Member, IEEE Abstract—A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented. The procedure is focused on the development of ultra-low-power ampliﬁers re- quiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed a CMOS OTA in a 0.35- technology that occupies only , is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 with the 200 pF load. Comparison with prior art shows an improvement factor in the ﬁgures of merit higher than 5. Index Terms—CMOS analog integrated circuits, low-power de- sign, multistage ampliﬁers, operational transconductance ampli- ﬁers, subthreshold operation. I. INTRODUCTION T HE REDUCTION of power consumption is a crucial task for battery-operated applications, such as energy-har- vested-operated microsensor nodes, biomedical implantable devices and microsystems in general [1]–[6]. To satisfy the ultra-low-power demand, the use of MOS tran- sistors operating in the subthreshold (or weak inversion) re- gion has become a classical design methodology since the mid 1970s [7]. This approach is proﬁtably adopted when the main design constraints are both ultra-low-power consumption and low-voltage operation. As threshold voltages do not decrease in the same proportion as supply voltages, exploitation of the sub- threshold region increases the allowable signal swing. Further- more, a MOS transistor operated in the subthreshold region ex- hibits the highest transconductance efﬁciency, [7], and the lowest distortion [8]. As a drawback, subthreshold operation leads to reduced bandwidth and larger drain current mismatch Manuscript received December 05, 2014; revised February 11, 2015; ac- cepted February 25, 2015. Date of publication April 09, 2015; date of current version May 25, 2015. This paper was recommended by Associate Editor P.-I. Mak. A. D. Grasso, G. Palumbo and S. Pennisi are with the DIEEI (Dipartimento di Ingegneria Elettrica Elettronica e Informatica), University of Catania, I-95125 Catania, Italy (e-mail: agrasso@dieei.unict.it; gpalumbo@diees.unict.it; spen- nisi@dieei.unict.it). D. Marano is with OACT (Osservatorio Astroﬁsico di Catania), within INAF (Istituto Nazionale di Astroﬁsica), I-95123 Catania, Italy (e-mail: davide.marano@oact.inaf.it). Color versions of one or more of the ﬁgures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identiﬁer 10.1109/TCSI.2015.2411796 (this means that proper offset compensation schemes should be adopted when offset is a critical design speciﬁcation). In this low voltage context, to guarantee an increased input swing, tech- niques exploiting the bulk as input node (bulk driving), previ- ously proposed for MOS devices in saturation [8], have also been extended to the subthreshold [10]–[15]. A disadvantage of this approach is that the bulk transconductance is lower than the gate transconductance and that the bulk ﬁnite input resis- tance and leakage currents prevent the use of the body-driven technique in many contexts, such as the switched-capacitor ap- proach [16]. Other methods exploit the bulk of the MOS dif- ferential pair as a control terminal in order to set the quiescent current and provide common-mode control, removing the need of the tail current generator [17], [18]. It should be observed that the low bandwidth achievable by subthreshold MOS devices is only slightly compensated by the higher MOS transition frequency of scaled technologies. Nev- ertheless, subthreshold region is particularly suitable in wireless sensor networks, biomedical applications and in those applica- tions where speed is not a concern, e.g., for bandwidth speciﬁ- cations in the range of a few kilohertz [19], [20]. For this reason, subthreshold techniques are becoming more popular in the im- plementation of OTAs and other analog building blocks pow- ered from sub 1-V supplies and with current consumptions in the order of a few hundred nanoamperes [16], [18]–[23]. More- over, among the applications where subthreshold ampliﬁers can be applied, low dropout regulators may represent a case in which a high capacitive load and DC gain are required [1]. As detailed in Appendix B, the gain of the elementary common-source stage in subthreshold region is only dependent on a technological parameter [24]. Thus, in general, in an ampliﬁer fully working in the subthreshold region, the overall gain is determined by the architecture (i.e., number and type of gain stages), regardless of transistors aspect ratios. Considering that cascode topologies cannot be fully exploited due to the stringent low-voltage requirements, the only way to obtain DC gains higher than 100 dB is through ampliﬁer topologies entailing three cascaded elementary gain stages. Note that in all the previous subthreshold ampliﬁers (reported in the refer- ences), the DC gain is always below 70 dB, except for [14] and [16], where gain is about 90 dB and 80 dB, respectively. In this paper, we present a well-deﬁned design methodology for an ultra-low-power three-stage ampliﬁer working in the subthreshold region, which requires low silicon area and allows 1549-8328 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.