1 Real Time Pipelined System Design Through Simulated Annealing M.Coli 1 , P.Palazzari 2 1 Università "La Sapienza" - Dpt. di Ingegneria Elettronica - Via Eudossiana 18, 00184 Roma Fax +39-6-4742647, E-mail coli@die.ing.uniroma1.it 2 ENEA - HPCN project- C.R:Casaccia - Via Anguillarese 301 - 00060 S.Maria di Galeria (Roma) Fax +39-6-30483537, E-mail palazzari@casaccia.enea.it Abstract. This paper concerns with automatic pipeline implementation of a program subject to some real time (RT) constraints; the program is described through a Control Data Flow Graph (CDFG). We have developed a mapping methodology which assigns to each instruction of CDFG a time step and a HW resource for its execution. We have defined the space Ω of all the possible feasible mappings, as well an adjacency criterion on it and a cost function evaluating the quality of the mappings. We have minimized the cost function through a Simulated Annealing algorithm. The minimization process returns a mapping which satisfies all RT constraints, has minimal schedule length and minimal HW resource requirement. In order to show the capabilities of the proposed mapping methodology, we apply it to a graph with 50 nodes and several RT constraints: the obtained mapping gives a pipelined execution modality of the graph which satisfies all the given RT constraints. Keywords: allocation table, real time, pipeline system, simulated annealing. 1 Introduction In real time (RT) environment often data must be read from external channels at a given frequency and results must be produced within a prefixed time. Program controlling RT environment can be represented through a Control Data Flow Graph G=(N,E), where N={n i , i=1,2,...,n} is the node set and E={(n i ,n j ) | n i ,n j ∈N, n j uses a result produced by n i } is the internode communication set; each node n i is an operation of the program and each edge (n i ,n j ) represents a data or a control dependence. Some nodes of G are subjected to RT constraints which can be described through the following RTC set RTC = {(n i ,t ni ) | n i must finish its execution within t ni }; we assume the beginning of G computation to be triggered by the arrival of external data at t=0. In this work we consider the case in which data arrive in sequence from external channels with a given interarrival period ∆t. In order to satisfy all the RT requirements, G must be executed in a way such as no data in the (possibly infinite) input sequence is lost and all the timing constraints contained in RTC are satisfied. Often RT requirements are very strong and can be satisfied only by using dedicated HW devices. The iterative arrival of input data, and the consequent iterative execution of instances of G, makes very attractive the use of pipelining techniques which allow the overlapped (in time) execution of different instances of G. In the paper we will present a method to determine a) a (nearly) minimum set S of HW devices sufficient to execute G and b) a scheduling modality which allows the pipelined execution of G on S and satisfies all RT constraints. As scheduling tasks is a NP-complete problem [15], a lot of works were published about scheduling in RT environment ([8]-[11]) or in parallel systems ([12]-[14]). All these works do not consider the pipelined execution of G. A lot of papers were also published on pipelined system design (see [1]-[5] for example), but in this case RT requirements were not taken into account. This paper is the first, to our knowledge, which