Composite ULP diode fabrication, modelling and applications in multi-V th FD SOI CMOS technology David Levacq a, * , Christophe Liber a , Vincent Dessard b , Denis Flandre a a Microelectronics Laboratory, Universit e catholique de Louvain (UCL), Place du Levant 3, B-1348 Louvain-la-Neuve, Belgium b CISSOID, Place des Sciences, 4 bte 7, B-1348 Louvain-la-Neuve, Belgium The review of this paper was arranged by Prof. S. Cristoloveanu Abstract We present new SOI basic circuit cells architectures for ultra-low power (ULP) applications that use transistors in very weak inversion. These cells take advantage of the possibility to obtain multi-threshold transistors in fully depleted (FD) SOI CMOS with no additional cost. In particular, a new composite ULP diode is proposed and modelled. It has been fabricated on 0.18 and 2 lm FD SOI technologies and demonstrated a reduction of leakage currents by four orders of magnitude compared to standard MOS diode implementation. We demonstrate that the ULP diode can be used to realize memory cells that present strongly reduced static power consumption compared to standard SRAM cells and can work under 0.5 V supply voltage. As particular application, simulations of ULP memory latches used as level- keepers in MTCMOS circuits to maintain information on floating nodes during standby mode demonstrate static power savings of 20% when compared to the best traditional schemes with comparable speed performance. Finally, measurements show that the new proposed ULP cells keep functionality at high temperature. Ó 2004 Elsevier Ltd. All rights reserved. Keywords: SOI; Low power; Diode; Memory; MTCMOS 1. Introduction In standard CMOS technologies, threshold voltages (V th ) of n and p-MOSFETs are generally symmetrical in order to reduce static power consumption and short circuit currents in digital circuits. Symmetry is obtained thanks to two different channel implantations. In a fully depleted SOI CMOS process (FD SOI), we can easily obtain transistors with different threshold voltages by masking, inverting or adding channel implantations of n and p-MOSFETs. The direct access to different thresh- old voltages in SOI presents several advantages. First of all, it considerably enlarges the design window for analog circuits. In particular, the possibility to obtain non-doped, or intrinsic, transistors leads to strongly improved analog performance in terms of speed, dis- tortion, power consumption... [1]. Digital circuits also take advantage of the availability of different threshold voltages. Multi-threshold CMOS (MTCMOS) circuits combine low-V th and high-V th transistors to achieve an optimal tradeoff between speed and power consumption performance in low-supply voltage circuits. In this paper, we first discuss some process aspects to obtain multi-V th transistors in SOI. We then demonstrate new basic circuits targeting for ultra-low power applications (ULP) that exploit the combination of various V th transistors. In particular, we propose a novel diode architecture with strongly reduced leakage current and its analytical model supported by experimental results in deep-submicron FD SOI. A direct application of the new diode is the realization of an original memory cell that achieves a strong reduction of the static and dy- namic power consumptions by using transistors in very weak inversion regimes. It is intended for low-supply * Corresponding author. Tel.: +32-1047-25-64; fax: +32- 1047-25-98. 0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2003.12.016 Solid-State Electronics 48 (2004) 1017–1025 www.elsevier.com/locate/sse