Principles of new method of optimisation, design and modelling of pipeline A/D converters K. Je ˛ drzejewski * , A.A. Platonov Institute of Electronic Systems, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warsaw, Poland article info Article history: Received 29 June 2007 Received in revised form 12 July 2008 Accepted 11 September 2008 Available online 25 September 2008 Keywords: Pipeline A/D converter Architecture Modelling Optimisation abstract The paper presents the foundations of a new approach to design, optimisation and model- ling of a new class of pipeline analogue-to-digital converters (PADC). The approach employs the results of analytical and applied research on the concurrent optimisation of the analogue and digital parts of adaptive estimation systems. Application of the approach allows to modify the known architecture and principles of conversion used in conventional PADC in the way significantly improving quality of conversion. Particularities of function- ing of new PADC were studied in advanced simulation experiments, which confirmed the results of analytical investigations. Special attention was paid to comparison of the perfor- mance of new and known PADC and assessment of potentially achievable benefits. Ó 2008 Elsevier Ltd. All rights reserved. 1. Introduction Recently, pipeline A/D converters (PADC) have become a widely used class of A/D converters (ADC) most appropri- ate for applications, requiring relatively high bandwidth (speed of conversion) and resolution [1–3]. High speed of conversion in PADC is a result of the multi-stage, pipeline principle of samples conversion (see Section 2). In the pa- per, a new class of ‘‘intelligent” pipeline A/D converters (IP ADC) is proposed. The architecture of IP ADC and the principle of conversion are based on the results of the ap- proach [4,5] permitting concurrent (simultaneous) optimi- sation of the analogue, which is adjusted adaptively, and digital parts of estimation systems. The approach allows to determine analytically the close-to-optimal, under given conditions, structure and values of the parameters of the converter which requires minimal heuristic corrections to guarantee maximal speed and accuracy of conversion un- der given permissible probability of saturation. Similar approach was applied to optimisation and design of the laboratory prototype of intelligent cyclic A/D converter (IC ADC) [6–8], realised in CMOS AMS 0.35 l technology, nowadays investigated. Unlike IC ADC, application of analytical approach [4,5] to PADC optimisation and design leads to radical changes in the architecture and principles of conversion. First of all, this is a resignation from the common for conventional PADC method of the input signal codes computing in the form of a sum of shifted low-bit binary words delivered by sequential stages (see also [6–8]). In IP ADC, these codes are computed in each stage of conversion as long-bit bin- ary words of fixed length N comp (N comp = 16  32-bits is the number of bits in binary words representing the codes of the sample computed in the digital part, and should be 3–5 bits greater than the required resolution of IP ADC). This enables a uniform mathematical description of the analogue and digital parts of IP ADC in the terms of con- tinuous values models and variables, which creates a possibility to compute the codes using optimal adaptive estimation algorithms proposed in [4,5]. Also, application of the long-bit codes presentation and computing permits to remove, inevitable in known pipeline ADC, constraints on the gain coefficients of amplifiers in particular stages 0263-2241/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.measurement.2008.09.009 * Corresponding author. Tel.: +48 22 234 79 52; fax: +48 22 825 23 00. E-mail addresses: kala@ise.pw.edu.pl (K. Je ˛ drzejewski), plat@ise.pw. edu.pl (A.A. Platonov). Measurement 42 (2009) 1195–1202 Contents lists available at ScienceDirect Measurement journal homepage: www.elsevier.com/locate/measurement