-page number- ISOCC 2015 Static Leakage Control in Null Convention Logic Standard Cells in 28 nm UTBB-FDSOI CMOS Jeeson Kim Electrical & Computer Engineering RMIT University, Melbourne, Australia Matthew M. Kim Electrical & Computer Engineering RMIT University, Melbourne, Australia Paul Beckett Electrical & Computer Engineering RMIT University, Melbourne, Australia Abstract— A key advantage of asynchronous systems, in which the clock is re-placed by local handshaking signals between func- tional units, is their ability to operate correctly across a wide range of conditions including supply, temperature, aging and manufacturing variability. In this letter, we describe the design, simulation and layout of a representative example of a quasi- delay-insensitive asynchronous logic family, Null Convention Logic, based on a 28nm ultra-thin body and box, fully depleted silicon-on-insulator (UTBB-FDSOI) process. This technology choice supports a flexible trade-off between leakage power and performance using substrate/well bias, including a potential for temperature dependent biasing. Simulation results indicate that it is possible to reduce the effects of increased temperature on leakage current by more than 2X with a small impact (~10%) on propagation delay. Keywords-Asynchronous circuits; Null Convention Logic; CMOS leakage; UTBB-FDSOI I. INTRODUCTION Asynchronous systems, in which the clock is replaced by local handshaking signals between functional units, are receiv- ing more attention due to their potential for reduced power consumption, lower susceptibility to electromagnetic interfe- rence (EMI), higher robustness in the face of device variability and ease of design reuse and in particular, their ability to oper- ate seamlessly over a wide range of environmental conditions such as supply and temperature [1]. In this paper, we describe the design, simulation and layout of a simple example of a Null Convention Logic gate based on a 28nm ultra-thin body and box, fully depleted silicon-on-insulator (UTBB-FDSOI) process [2] that particularly targets portable and multimedia applications. In this process CMOS transistors are formed within a 7nm thin layer of silicon over 25nm of buried oxide (BOX), which ensures good electrostatic control with lower threshold variability compared to bulk CMOS. Further, “back- gate” biasing (i.e., of the well or substrate under the buried oxide) can be used to trade off speed against leakage power. II. DESIGN OF STANDARD CELL LIBRARY A. NCL Circuits The “native” gate topology in NCL is the “m-of-n” thre- shold gate that exhibits state behaviour (hysteresis) such that its output will only transition in response to a complete set of inputs (i.e., completely data or completely null). For this rea- son, individual NCL gates are much more complex than sim- ple Boolean logic. For example, while the TH22 (“2-of-2”) is functionally equivalent to a simple AND (y = a AND b), a fully static implementation of the TH22 comprises 12 transis- tors divided into four blocks (Fig. 1). (a) (b) Figure 1. Implementation of NCL circuit. (a) Basic structure of the static implementation of NCL circuits. (b) Example TH22 schematic. Figure 2. Example TH22 standard cell layout in 28nm UTBB-FDSOI B. 28 nm Layout Style The layout of these standard cells was constrained to match the fixed height of the existing cells in the process kit. Thus our NCL library is based on a template of 1.2µm cell height and 0.136 × N cell width, where N depends on the gate complexity. The full library comprises 34 gate cells: 27 fundamental thre- shold gates defined for combinations of up to four inputs and seven additional gates. Fig. 2 shows an example layout for the TH22 with an overall width of 1.2µm and height of 1.408µm.