Power Analysis and Optimization for High-Speed 10 Transceivers (Invited Paper) Kwangmo Jung, Yue Lu, Elad Alon University of California at Berkeley Email: { kwangmo,yuelu,elad } @eecs.berkeley.edu Abstract-This paper analytically optimizes the overall power consumption of the signaling path of a high-speed link uti lizing a source-series terminated (SST) transmitter, either a receive continuous-ime linear equalizer (CTLE) or transmit pre emphasis, and operating over a simple single-pole channel. The analysis derives the optimal allocation between transmit swing and receive gain as well as the allocation of power consumption between the two sides. The analysis also shows that the pre-driver overheads inherent in implementing programmable transmit pre emphasis make the receive CTLE a substantially more power eicient solution. I. INTRODUCTION Modern high-speed transceivers must provide up to several 1O's of Gbps with low bit error rate (BER) while maintaining good power eiciency. This stringent requirement forces de signers to use low-power circuitry as well as simple equaliza tion schemes. While there have been signiicant improvements in link power-eiciency over the last several years [ I] [2], relatively little analytical work has been done to highlight the underlying tradeofs behind the choice of link rchitecture. An SST transmitter is a popular choice to save signaling power due to its higher efective impedance than a current mode transmitter. However, especially when additional cir cuitry for a transmit FIR ilter is implemented, pre-driver dynamic power becomes signiicant. To better quantify its power advantage, we begin this paper by analyzing the power consumption of an SST transmitter. As we will see in the analysis of the following section, a CTLE can provide a much lower power solution for equal ization. Based on these analyses, we next derive the optimal power allocation between the transmitter and the receiver using a single-pole channel model. Finally, practical concerns in achieving the predicted power eiciency will be highlighted. II. SOURCE-SERIES TERMINATED DRIVER Most power optimized links utilize low transmit swings (typically ,20OmV amplitude), making N-over-N low-swing voltage-mode transmitters (Fig. 2(a» popular. In the simplest case, the pre-driver consists of a bufer chain with a per-stage fan-out F and the irst-stage input capacitance constrained to Gin ' To maintain a given termination resistance RT over various voltage swings and PVT conditions, an impedance stabilization loop must be utilized. This loop typically controls the gate voltage of (M I-M4) by varying the supply voltage of elk Fig. l. Link with a single-pole channel the last stage in the pre-driver. Since the range of the gate conrol supply voltage is usually designed to remain close to the nominal supply Vdd in order to improve delay matching between the pull-up and pull-down paths, for simplicity we will assume that the inal stage supply is always simply Vdd. To transmit a data sream with diferential amplitude of VT x, the inal driver's supply voltage Vdrv should be set to 2VT x. Assuming Vdrv is generated by a linear regulator, the ransmitter's static power consumption is: p _ VTXVdd st,TX - 2RT ( I) In order to accurately predict the power consumption of the complete transmitter, the dynamic power dissipation must also be considered. One notable contributor to this is the input loading Gfin of the inal driver, which is the sum of the gate capacitance of M I-M4. Since transmit swing is usually small for a power-optimized link, we assume that the Vc s of M I-M4 are all roughly equal to Vdd, and hence. Gfin = 4Gg,MI-M4 (2) Another contributor is the pre-driver's bufer chain. As the input and the load capacitance of the chain are given, the total switching capacitance in the pre-driver is expressed by: 1 + YD Gp re = 2 (2Gg ,MI- M4 - Gin ) F _ 1 (3) where YD is the drain to the gate capacitance ratio. Assuming simple CMOS inverters, the total power consumption of the transmitter is': 2 VTXVdd Ptot,vmTX = adfbitVdd (Gp re + Gfin ) + 2RT (4) where ad is the activity factor and fbit is the data rate. 1 Switching the load capacitance of the inal driver also adds to the dynamic power consumption. However, since the waveform at the transmitter should be fully settled, this dynamic power consumption can be ignored since it will be small compared to the static power consumption of the output stage. 978-1-61284-857-0/11/$26.00 92011 IEEE