3088 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 8, AUGUST 2008 Capacitor Balance Issues of the Diode-Clamped Multilevel Inverter Operated in a Quasi Two-State Mode Grain P. Adam, Stephen J. Finney, Ahmed M. Massoud, and Barry W. Williams Abstract—A new operational mode for diode-clamped multi- level inverters termed quasi two-level operation is proposed. Such operation aims to avoid the imbalance problem of the dc-link ca- pacitors for multilevel inverters with more than three levels and re- duces the dc-link capacitance without introducing any significant voltage ripple at the dc-link nodes. The proposed operation can be generalized for any number of levels. The validity of the proposed multilevel inverter operational mode is confirmed by simulations and experiments on a prototype five-level diode-clamped inverter. Index Terms—Multilevel inverter, neutral point clamped. I. I NTRODUCTION S ERIES connection of semiconductor devices is a solution for achieving higher converter voltage ratings; however, devices suffer from unbalanced static and dynamic voltage sharing, and the output voltage has a high dv/dt. A multilevel inverter can overcome these disadvantages. The multilevel concept is based on a step approximation to a sinusoidal voltage [1]–[3]. Multilevel inverters belong to the inverter circuit family, where the output voltage comprised more than two intermediate discrete voltage levels. The purpose of these circuits is to generate a high-voltage waveform using lower voltage rating switching devices connected in series. Typ- ically, the series-connected devices are sequentially switched, producing an output pattern that contains discrete predefined steps. Each switch blocks its rated normal voltage, but the total output voltage can be much higher [4], [5]. Multilevel inverters, in general, have advantages over conventional two- level inverters due to their ability to handle high voltage with minimum voltage stress on the switching devices, have a low harmonic content in the output voltage, generate lower dv/dt, and have a lower common-mode voltage, which results in reduced stress on motor bearings in drive applications [6], [7]. In diode-clamped multilevel inverters, device voltage sharing is achieved via the clamping diodes, whereas lower dv/dt is achieved with stepped voltage changes. However, the diode- clamped multilevel suffers from dc-link capacitor unbalance [7], [8]. Manuscript received November 16, 2007; revised March 18, 2008. Published July 30, 2008 (projected). The authors are with the Department of Electronic and Electrical Engineer- ing, Strathclyde University, Glasgow, G1 1XQ, U.K. (e-mail: grain.adam@ eee.strath.ac.uk; ahmed.massoud@eee.strath.ac.uk; s.finney@eee.strath.ac.uk; barry.williams@eee.strath.ac.uk). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2008.922607 To balance the dc-link series capacitors, two main balancing approaches have been proposed: 1) the use of auxiliary bal- ancing networks and 2) the manipulation of redundant switch states. Auxiliary networks achieve capacitor balance by the transfer of energy between the capacitors [6], [9]–[11] or the direct transfer of energy from the link supply. The inclusion of such networks significantly increases the complexity of the inverter system. The duty placed on the auxiliary circuits depends on the level of real power drawn from the inverter and the modulation index. It is found that such circuits require similar ratings to those of the main power inverter (same voltage and typically 10% of the rated current) [10]. Pulsewidth modulation (PWM) for three-phase multilevel inverters is complex but offers a number of redundant switch states. These redundant states can be used to help balance the link capacitor voltages [12]–[17]. This approach may minimize or eliminate the need for auxiliary balancing circuits but faces limitations in terms of modulation index range, degradation of output voltage quality, and switching loss increase. To avoid such balancing techniques, a new operational mode for the five-level diode-clamped inverter is presented. One leg of the five-level diode-clamped inverter circuit shown in Fig. 1(a) is used as a conventional two-level inverter with series- connected devices. The five-level clamping circuits are used as transient soft clamping snubbers to prevent switch overvoltage and to ensure transient voltage sharing between cells). The clamping circuits are active for a short dwell duration of a few microseconds. The sequential switching of devices during out- put phase transitions between −(1/2)V dc and (1/2)V dc dwell at the intermediate voltage levels −(1/4)V dc , 0, and (1/4)V dc . Thus, the intermediate voltage levels are used for soft voltage clamping and experience minimal charge loading. While this approach does not utilize the full potential of multilevel modulation, the system does present a practical compromise between the series connection of devices and full multilevel operation. Unlike conventional series device con- nection, matched power devices and gate drive delays are not necessary, and direct capacitive snubbers are not required. The production of a stepped voltage waveform means that the overall dv/dt of the stack is reduced while still allowing each device to switch at a rate compatible with minimum switching. Because the capacitor divider is primarily used as a transient clamping network, the energy drawn from these capacitors is a small fraction of that with full multilevel operation, as is the size of the multilevel clamping components. 0278-0046/$25.00 © 2008 IEEE