448 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 31, NO 3, MARCH zyx 1996 Special Issue rief Pape zyx A Module Generator for High-speed CMOS Current Output Dig i tal/Arialog Converters Robert R. Neff, Paul R. Gray, and Albert0 Sangiovanni-Vincentelli Abstract-A module generator (DSYN) creates optimized dig- itdanalog converter (DAC) layouts given a set of specifica- tions including performance constraints, a description of the implementation technology, and a set of design parameters. The generation process consists of a synthesis step followed by a layout step. During synthesis, a new constrained optimization method is coupled with combination of circuit simulation and DAC design equations. The layout step uses stretching and tiling operations on a set of primitive cells. Prototypeshave been demonstrated for zyxwvu an 8-b, lOO-MS/s specification, driving a 37.5-ohm video load, and a static 10-b specification, driving a 4 mA full-scale output current. Both designs use a 5-V supply in a 1.2 zyxwvuts pm CMOS process. I. INTRODUCTION N mixed-signal integrated circuits, the analog part of the design often occupies a small portion of the physical die area but’ requires a disproportionately large amount of the design effort and time. Following a digital domain paradigm, analog circuit synthesis has been proposed to substantially reduce design time [1]-[4]. This approach is intended for a wide class of commonly used analog circuits, but as such, does not incorporate specific knowledge of the particular device being designed. These methods have proven useful for application to the most common building blocks, such as amplifiers and comparators, which tend to have a relatively small number of large devices, and matching constraints between pairs, but not across large numbers of elements. For other, more complex blocks, the general synthesis approach is a poor match to the problem. A second approach consists of developing several synthesis tools, each optimized for a particular class of circuits, such as switched capacitor filters, op-amps, or analog/digital converters (ADC’s) zyxwvutsr [5]-[8]. In either case, the goal is to generate blocks that are competitive with manual design in performance and die area. The best test of these analog circuit synthesis methodologies is to follow designs through the complete cycle, including design specific inputs and results from fabricated devices. Generation of mixed-signal analog blocks can be ap- proached in several ways. In the top-down, hierarchical Manuscript received October 18, 1995; revised December 15, 1995. This work was supported by the Semiconductor Research Corporation under Grant 94-DC-324. R. R. Neff was with the University of Califomia, Berkeley, CA. He is now with Hewlett Packard Company, Palo Alto, CA 94304-0867 USA. P. R. Gray and A. Sangiovanni-Vincentelli are with the Department of Electrical Engineering and Computer Sciences, University of Califomia, Berkeley, CA 94720 USA. Publisher Item Identifier S 0018-9200(96)02462-6. approach, proposed in [9], constraint values are passed down through layers of the design, with the bottom layer corresponding to the transistors. This approach was initially applied to a current-switched digitaUanalog converter (DAC) example, and has also been used to build an oversampled ADC [lo]. The main goal of the hierarchical approach is to obtain reliably and quickly a design that satisfies all constraints. When, in addition to satisfying constraints, a highly optimized circuit with respect to area and speed is required, then a “flat” methodology may prove more effective. In a flat approach, many design variables are optimized at once against the complete design specification. When a complex circuit behavior is difficult to separate and evaluate hierarchically, a flat approach is the only option. Of course there are limits to our design optimization capabilities-as the number of design variables increases, a flat method becomes more difficult. In this paper, a nonhierarchical approach is applied to the current-switched DAC function, allowing simultaneous optimization of architecture and device level design variables, and easy incorporation of all aspects of performance, including layout related parasitics when predicting static and dynamic performance. 11. MODULE GENERATION METHODOLOGY Fig. 1 illustrates the module generation methodology. Input data is separated into information classes, which are used dur- ing the optimization step to find the best set of design variables. The design variables are then passed to the layout program, creating the DAC module. Design optimization can be further decomposed into two parts, the optimization algorithm and the design estimation process. The input data is partitioned into design constants, perfor- mance specifications, and design variables. Typically, design variables are continuous variables, but in the case of DAC module generation, there are several variables which must have discrete values. Two examples of this are the number of least significant bits (LSB’s) per DAC segment, which must be a power of two, and the number of bias cells, which must be an integer. In addition to these “intrinsic” integer variables, we force device dimensions to fall on the L,i,/2 grid required by our layout tools, so that all design variables are constrained to be integers. The design estimation step predicts the performance of the circuit, including process variation, device mismatch, and 0018-9200/96$05.00 zyxwvut 0 1996 IEEE