IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 12, DECEMBER 2011 4241 Asymmetrically Doped FinFETs for Low-Power Robust SRAMs Farshad Moradi, Member, IEEE, Sumeet Kumar Gupta, Student Member, IEEE, Georgios Panagopoulos, Student Member, IEEE, Dag T. Wisland, Member, IEEE, Hamid Mahmoodi, Member, IEEE, and Kaushik Roy, Fellow, IEEE Abstract—We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read–write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%–8.3% improvement in read static noise margin (SNM), 4.1%–10.2% higher write mar- gin, 4.1%–8.8% lower write time, 1.3%–3.5% higher hold SNM, and 2.1–2.5× lower cell leakage at the cost of 20%–23% higher access time. There is no area penalty associated with the proposed technique. Index Terms—Asymmetric doping, FinFET, SRAM. I. I NTRODUCTION A GGRESSIVE device scaling has led to statistical vari- ability in device parameters and increased short-channel effects (SCEs) [1], [2]. Thinner gate oxide helps to improve the SCEs. However, thinner gate oxide leads to exponentially higher gate leakage. Thus, to overcome SCE, different candi- date transistor structures have been investigated to replace the bulk MOSFETs [3]–[10]. Among them, FinFETs are consid- ered to be a promising candidate for scaled CMOS devices in scaled technology nodes. FinFETs show increased immunity to SCE due to improved channel control by the gate voltage [11]. Furthermore, threshold voltage (V TH ) can be easily controlled Manuscript received March 1, 2011; revised August 21, 2011; accepted September 14, 2011. Date of publication October 19, 2011; date of current version November 23, 2011. The review of this paper was arranged by Editor H. S. Momose. F. Moradi is with the Integrated Circuit and Electronics Laboratory, Aarhus School of Engineering, Aarhus University, 8000 Aarhus, Denmark (e-mail: famo@ase.au.dk). S. K. Gupta, G. Panagopoulos, and K. Roy are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: guptask@purdue.edu; gpanagop@purdue.edu; Kaushik@purdue.edu). D. T. Wisland is with Novelda AS, 0319 Oslo, Norway, and also with the Nanoelectronics Research Group, University of Oslo, 0316 Oslo, Norway (e-mail: dagwis@ifi.uio.no). H. Mahmoodi is with the School of Engineering, San Francisco State University, San Francisco, CA 94132 USA (e-mail: Mahmoodi@sfsu.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2169678 by engineering the metal gate work function. Moreover, V TH variations due to random dopant fluctuation in the channel region are reduced due to almost intrinsic channel doping [12], [13]. Since memories take up 80% of the die area in high- performance processors, there is a need for high-performance, low-leakage, and highly robust SRAMs [14]. Unfortunately in scaled technologies, particularly under scaled supply volt- ages, the read and write stabilities of SRAMs are affected by process variations. Due to a large number of small geometry transistors in a memory array, process variations have a sig- nificant impact—leading to possible read, write, and access failures, particularly at lower supply voltages. Furthermore, in conventional 6T SRAMs, the conflict between read and write stabilities is an unavoidable design constraint [15] and aggravates the effect of process variations on SRAM stability and performance. One option to improve the conflicting read and write re- quirements is to decouple the read/write operations, for which researchers have considered new bit cells such as 8T and 10T [16], [17]. However, such cells come with an increased area. Several other techniques have been proposed to improve the 6T SRAM stability, performance, and/or leakage by introduc- ing optimized devices [18]–[28]. Although these techniques improve device characteristics, the tradeoffs are not clearly ad- dressed, and improvement in conflicting read and write margins is marginal. An interesting design option to achieve mitigation of read–write conflict is to introduce asymmetry in the access transistor such that unequal currents flow for positive and neg- ative V DS ’s. One such technique uses asymmetric halo in bulk MOSFETs [27]. However, this leads to aggravation of SCEs and an increase in leakage of the device. For FinFETs, another technique has been proposed in [28] in which asymmetric drain underlap is introduced in the device (by employing asymmetric spacers). In this technique, the drain-induced barrier lowering (DIBL), subthreshold swing (SS), and subthreshold leakage current are improved. However, asymmetric spacer FinFETs may lead to increased variations in such devices. In this paper, we propose to achieve asymmetry in the device by unequally doping the drain and source terminals of FinFETs [asymmetrically doped (AD) FinFETs]. Depending on the de- vice biasing, the proposed modification to the device structure leads to different currents from the source and the drain sides, respectively. Based on that, we design a FinFET SRAM bit cell to simultaneously improve read and write margins in scaled 0018-9383/$26.00 © 2011 IEEE