HMSR : A Hybrid Network-on-Chip Topology Synthesis Based on Star-Ring-Mesh at System Level Abid Noureddine Electronics and Microelectronics Laboratory University of Monastir, Tunisia Abid_noureddine@live.fr Attia Brahim 1 ; Abdelkrim Zitouni 2 Electronics and Microelectronics Laboratory, University of Monastir, Tunisia 1 , Colledge of Education in Jubail, University of Dammam, Dammam 31441, KSA 2 brahim.attia@yahoo.fr ; azitouni@uod.edu.sa Abstract— The Network-on-Chip (NoC) paradigm has been proposed as a revolutionary methodology to incorporate a great number of multiple cores of a given application into a single SoC. We can have an application with significant amount of locality of communication. The bandwidth locality is required to be present at multiple levels. We suggest extracting the locality communication of sub tasks of applications. To this end, it is essential to provide a suitable NoC topology that exploits the locality of communication resourcefully. This can be done by using many sub-networks for local communication and one network for global communication. In this paper, we propose two new hybrid topologies that take advantage of such communication locality. It can be personalized by the combination of the benefits of the 2D-Mesh, STAR and RING architectures HMSR. These new hybrid topologies are called respectively a Hybrid Locally Mesh Globally Star-Ring (HLMGSR) and Hybrid Locally Star-Ring Globally Mesh (HLSRGM). These two hybrid topologies use the Star-Ring and mesh graphs as the basic building blocks, and investigate the topological properties of the resulting family of networks. We have developed a transaction level model of communication components of NoC such as link, routers which is implemented in SystemC TLM2.0. The experimental results show that for a network size equal to 128, the proposed hierarchical topology HLMGSR provides an area increase of 27% over HLSRGM, 7% over the mesh. The area increase is about 19% between HLMGSR and mesh topologies. For a network size which is greater than or equal to 64 nodes, the lowest average latency is provided by the two proposed hybrid topologies for different injection rates. The results show as well that for a network size which is greater or equal to 64 nodes with the uniform traffic pattern with a lower injection rate, the best throughput is provided by the HLSRGM, but for higher injection rate the HLMGSR provides the highest throughput. Keywords-component; Network on chip, Hybrid NoC, Locality of Communication, TLM 2.0. I. INTRODUCTION State-of-the-art System-on-Chip (SoC) is made of hundreds of processing elements, while trends in design of the next generation of SoC point to the combination of thousand of processing elements, necessitating high performance interconnect for high throughput communications. Nowadays, designing embedded products is difficult on account of the diversity and the complexity of applications. More computing power is needed to execute these applications. Also, many applications are time consuming with serial computing. In parallel computing, many processing or calculations can be done simultaneously operating on the principle that large problems can often be partitioned or divided into smaller ones, which are then executed simultaneously as cooperating processes, and required to be paralleled. One solution, widely used to provide more computing power, consists of designing multiprocessor system on chips (MPSoC) [1]. The shift to very high performance distributed multiprocessor systems-on-chip (MP-SoC) is the recognized route to reach the performance requirement for compute- intensive applications [2]. MPSoC requires high-speed communication between processors, which clearly relies on the existence of a fast and flexible interconnect network. To overcome the problems of complexity and scalability of inter communication platform of SoCs composed by hundreds of cores, Network on Chip (NoC) has emerged as a promising replacement for buses and dedicated interconnections. Network interconnections can be seen as a set of resources or cores (eg, processors, storage components), routers to transfer the packets, links to communicate with the adjacent routers, and network interfaces which represent a communication medium between routers and resources on a predefined topology. The topology is a very important feature in the design of NoC in order to improve the overall cost-performances such as throughput, hop count latency and area. Many network architecture interconnections that are based on different standard topologies have been studied recently for SoC such as 2D Mesh [2], Torus [3], Fat-Tree (FT) [4], Ring [5], Butterfly-Fat Tree (BFT) [6], Spidergon [7], Octagon [8]. These architectures are based on parallel concepts and distributed systems for interconnecting resources in a structured and scalable manner for ease of implementation. International Journal of Computer Science and Information Security (IJCSIS), Vol. 14, No. 9, September 2016 264 https://sites.google.com/site/ijcsis/ ISSN 1947-5500