See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/4100277 Improved FPGA-based dead time compensation for SVM inverters Conference Paper · January 2004 DOI: 10.1049/cp:20040367 · Source: IEEE Xplore CITATIONS 5 READS 249 5 authors, including: Silverio Bolognani University of Padova 244 PUBLICATIONS 5,919 CITATIONS SEE PROFILE P. Mattavelli University of Padova 383 PUBLICATIONS 8,145 CITATIONS SEE PROFILE Mauro Zigliotto University of Padova 107 PUBLICATIONS 2,593 CITATIONS SEE PROFILE All content following this page was uploaded by Mauro Zigliotto on 29 December 2016. The user has requested enhancement of the downloaded file. All in-text references underlined in blue are added to the original document and are linked to publications on ResearchGate, letting you access and read them immediately.