International Journal of Advancements in Computing Technology Volume 2, Number 5, December 2010 A Reduced-Area Reverse Converter for the Moduli Set {2ⁿ, 2ⁿ-1, 2 2n–1 –1} A. Sabbagh Molahosseini 1* , M. Kuchaki Rafsanjani 2 , S.H. Ghafouri 1 , M. Hashemipour 1 1 Department of Computer Engineering, Islamic Azad University, Kerman Branch, Kerman, Iran 2 Department of Computer Science, Shahid Bahonar University of Kerman, Kerman, Iran {sabbagh, ghafoori}@iauk.ac.ir, kuchaki@mail.uk.ac.ir * Corresponding author. doi:10.4156/ijact.vol2. issue5.6 Abstract The three-modulus residue number system (RNS) based on the moduli set {2 n , 2 n –1, 2 2n–1 –1} has been recently introduced. The modulo (2 n +1)-free feature of this set enables it to provide fast realization of modular addition and multiplication circuits of RNS arithmetic unit. But, the latest design of the RNS to binary (reverse) converter for the moduli set {2 n , 2 n –1, 2 2n–1 –1} relies on large hardware requirements which is not suitable for efficient VLSI implementation. This work presents an improved design of the reverse converter for the moduli set {2 n , 2 n –1, 2 2n–1 –1} based on new Chinese remainder theorem 2 (CRT-II). The proposed converter considerably reduces the converter area and requires less conversion delay compared to the previous design of the reverse converter for the moduli set {2 n , 2 n –1, 2 2n–1 –1}. Keywords: Computer Architecture, Residue Number System (RNS), Reverse Converter 1. Introduction The residue number system (RNS) makes it possible to implement arithmetic operations such as addition and multiplication in a parallel and fast architecture, due to its carry-free nature. The reverse converter decodes an RNS-represented number into its weighted binary form. Usually, the reverse conversion is the most complex and critical part of an RNS system, since a low-performance reverse converter can counteract the speed profit of the internal RNS arithmetic operations [1,2]. The moduli set {2 n , 2 n –1, 2 2n–1 –1} has been recently suggested in [3] to provide efficient implementation of the RNS arithmetic unit circuits and reverse converter at the same time. In other words, the absent of modulo (2n+1) in the set {2 n , 2 n –1, 2 2n–1 –1} results in decreasing the complexity of the RNS arithmetic unit, and also the simple multiplicative inverses can lead to a high-performance hardware design for reverse converter. However, the previous design of the reverse converter for the moduli set {2 n , 2 n –1, 2 2n–1 –1} that is introduced in [3] relies on large hardware requirements which can result in performance degradation of the total RNS system. In this work, a reduced-area reverse converter for the moduli set {2 n , 2 n –1, 2 2n–1 –1} using new Chinese remainder theorem 2 (CRT-II) [4] is presented. The proposed converter needs less hardware requirements with a slightly lower conversion delay than the converter of [3]. Besides, comparison the hardware complexity of the proposed design with the reverse converter of the moduli set {2 n , 2 n –1, 2 2n– 1 –1} [5] which has relatively the same dynamic range, show the considerable performance improvement in terms of hardware requirements and conversion delay. 2. Brief Background The RNS [1] is based on a moduli set {P 1 ,P 2 , …,P n }which consists of pair-wise relatively prime numbers. The dynamic range is defined as M=P1P2…Pn, which is refer to the interval of integer numbers that can uniquely be represented in RNS. A weighted number X<M has a unique representation in RNS as (x 1 , x 2 , …, x n ) where - 61 -