Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current Zhiyu Liu * , Volkan Kursun Department of Electrical and Computer Engineering, University of Wisconsin - Madison, Madison, WI 53706-1691, USA Received 1 June 2005; received in revised form 6 December 2005; accepted 3 January 2006 Available online 6 March 2006 Abstract A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology. q 2006 Elsevier Ltd. All rights reserved. Keywords: Domino logic; Dual threshold voltage; Gate oxide tunneling; Sleep switch; Subthreshold leakage current 1. Introduction Feature size scaling in MOSFETs requires reducing both the supply and threshold voltages. The lowering of threshold voltages leads to an exponential increase in the subthreshold leakage current. Several circuit techniques based on multiple threshold voltage (multiple-V t ) CMOS technologies are described in the literature for reducing the subthreshold leakage current [1–6,15,16]. The effect of these multiple-V t CMOS circuit techniques on the gate oxide leakage current characteristics, however, has not been explored until recently. In CMOS technologies with a gate insulator thicker than 20 A ˚ , gate oxide leakage current (I gate ) is orders of magnitude smaller than subthreshold leakage current [8,10]. Therefore, I gate has typically been ignored in the previous CMOS technologies with relatively thick gate oxide. I gate is caused by the direct tunneling of electrons and holes through the ultra- thin gate insulator layer. The tunneling probability of carriers increases with the scaling of the gate oxide thickness (t ox ) with each new technology generation. The tunneling current also has a strong dependence on the voltage difference across the gate dielectric layer. The variation of I gate with the supply voltage (V DD ) in two successive CMOS technologies (45 and 65 nm) is shown in Fig. 1. Scaling of the t ox by 3 A ˚ while advancing from the 65 nm technology node to the 45 nm technology node increases the I gate by 8.1! to 14.9! depending on the voltage difference across the gate oxide, as illustrated in Fig. 1. The t ox is in the range of 12 to 16 A ˚ in the current CMOS technologies [7,8,10]. Such a thin t ox leads to a significant gate tunneling current. The variation of the gate oxide and subthreshold leakage currents of an NMOS transistor with the supply voltage is shown in Fig. 2, a 45 nm CMOS technology. At the room temperature and the nominal supply voltage (V DD Z0.8 V), the I gate is 2.5!high than the subthreshold leakage current as illustrated in Fig. 2. As the aggressive scaling of t ox continues, the gate dielectric tunneling will soon become a primary leakage mechanism, particularly at the low die temperatures during long idle periods. New circuit techniques aimed at reducing both the subthreshold and gate oxide leakage currents are, therefore, highly desirable [18]. A circuit technique for lowering the gate oxide leakage current in domino logic circuits is presented in [11]. Using P-type (predischarge) domino is proposed in order to exploit the lower gate oxide leakage current characteristics of PMOS transistors as compared to NMOS transistors. The size of a P-type domino circuit, however, must be increased for achieving similar performance as compared to an N-type Microelectronics Journal 37 (2006) 812–820 www.elsevier.com/locate/mejo 0026-2692/$ - see front matter q 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2006.01.001 * Corresponding author. E-mail address: zhiyuliu@wisc.edu (Z. Liu).