Exploiting Rotational Symmetries for Improved Stacked Yields in W2W 3D-SICs Eshan Singh Electrical Engineering Stanford University esingh@stanford.edu Abstract – Three-dimensional Stacked Integrated Circuit packages interconnected using high speed Through-Silicon Via technology can be efficiently manufactured using a wafer-to-wafer stacking process. Efforts to mitigate degradation in the composite yield of the stacked die are primarily focused on matching defect maps while assigning the pre-tested wafers from the available wafer repository to individual wafer stacks. In this paper we show how rotational symmetry can be exploited to increase the number of available wafer defect maps by a factor of four, thereby significantly improving matching possibilities and hence yield. We further apply our approach to processor- memory stacks, with relatively high memory die yield from redundancy and repair, for which we also present new heuristic matching algorithms. Altogether, our new approach shows viable absolute yields, with yield improvement of better than 25% over stacking without any matching. This is a significant advance over earlier results. I. INTRODUCTION Three-dimensional Stacked Integrated Circuit packages (3D- SICs) comprising multiple stacked die interconnected using high speed Through-Silicon Via (TSV) technology are currently the focus of considerable development effort by the industry[1-4]. Such packages promise high integration density along with exceptional performance and low power because of the small (micrometer) dimensions and minimal electrical loading of the TSVs as compared to traditional off chip interconnections [5, 6]. Importantly, they also allow heterogeneous die, each implemented in its own individually optimized fabrication technology, to be compactly integrated together at efficiencies approaching monolithic fabrication [7, 8]. Three basic die stacking approaches can be used in fabricating 3D-SICs from traditionally processed wafers: Wafer-to-Wafer (W2W), Die-to-Wafer (D2W), and Die-to-Die (D2D) [1, 2]. Of the three, the W2W approach appears most attractive since considerable additional processing (including careful alignment) is required while fabricating the TSV connections during the die stacking and bonding steps associated with assembling the 3D-SICs. Handling, stacking and processing wafers in a W2W process rather than individual die required by the other approaches is generally much easier [9]. Unfortunately, W2W stacking suffers from the problem of yield degradation from compounding. For example, if the yield of good die on a wafer is 50%, the yield of a two such wafers stacked together can only be expected to be 25%, i.e. both stacked die at only 25% of the sites on the stacked wafer can be expected to be defect free. For a four wafer stack, the compound yield drops to an unacceptable 6.25%. Indeed, unless the 3D-SIC requires die from a heterogeneous mix of technologies, there is little benefit, from a yield perspective, in going to a 3-D technology over a single traditional die with a larger area. W2D or D2D stacked technologies, on the other hand, can allow individual pretested good die to be stacked, achieving much higher yields and silicon use efficiency. However, working with individual bare die during fabrication is extremely challenging. Consequently, techniques to mitigate the yield degradation from compounding in W2W technologies are being extensively researched [10-14]. The main approach being considered to improve the yield of stacked is wafer matching [11, 14]. This assumes the availability of a repository of pre tested wafers of each type to be stacked. The size of this repository is generally taken to be the one or two standard lots of 25 wafers of each type to be stacked. These can be reasonably expected to be available at the wafer stacking step during 3D-SIC fabrication. Wafers are then carefully matched in constructing the stacks so as to maximize the yield of defect free stacked 3D-SICs based on the known test results for each die location in the pretested wafers. However, in a fair evaluation of the effectiveness of such a wafer matching approach towards enhancing the 3D- SIC yield over random wafer stacking, it must be assumed that the matching procedure utilizes all the wafers in each lot, i.e. none of the wafers are scrapped or wasted.