448 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 2, FEBRUARY 2010 Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices Mayank Shrivastava, Student Member, IEEE, Maryam Shojaei Baghini, Senior Member, IEEE, Harald Gossner, Member, IEEE, and V. Ramgopal Rao, Senior Member, IEEE Abstract—In this paper, the optimization issues of various drain-extended devices are discussed for input/output applica- tions. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate per- formance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate–drain overlap improves the gate oxide relia- bility, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects. Index Terms—Drain-extended MOS (DeMOS), hot carrier, input/output, lightly doped drain MOS (LDDMOS), mixed signal, reduced surface field (RESURF), reliability. I. I NTRODUCTION N OWADAYS, electronic systems often have multiple semi- conductor chips fabricated in different CMOS technolo- gies handling different functionalities like voltage regulation, signal conditioning, data conversion, and digital processing. Many integrated circuits like system-on-chips (SOCs) consist of multiple embedded CMOS technologies. On the other hand, with the continued scaling of devices in advanced digital CMOS technologies, the power supply voltage is also getting scaled to reduce the power consumption and to meet the gate oxide reliability. Therefore, interfacing the semiconductor chips or subsystems on the chip, having different levels of supply voltage, and satisfying the speed and noise requirements are becoming crucial from the overall performance point of view. For example, a digital processing chip working with a supply voltage of 2 V may interact with a peripheral chip with a supply voltage of 12 V. The I/O circuit design should be allowed to span the entire design space that the logic design enjoys. How- ever, constraints like undesired leakage current paths between chips [1], [2], electrical overstress across the gate oxide [3], Manuscript received April 17, 2009; revised November 2, 2009 First pub- lished December 8, 2009; current version published January 22, 2010. The work of M. Shrivastava was supported by an Infineon Fellowship at Indian Institute of Technology Bombay, Mumbai, India. The review of this paper was arranged by Editor H. S. Momose. M. Shrivastava, M. Shojaei Baghini, and V. R. Rao are with the Center for Nanoelectronics, Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India (e-mail: mayank@ee.iitb.ac.in; rrao@ee.iitb.ac.in). H. Gossner is with Infineon Technology AG, 81609 Munich, Germany (e-mail: Harald.Gossner@infineon.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2009.2036796 and hot carrier degradation [4] in I/O design take away the flexibility. One of the bottlenecks for introducing CMOS I/O circuits is their susceptibility to electrostatic discharge (ESD). It is due to both the gate oxide breakdown and junction-degradation- related problems, caused by the decreased oxide thickness and increasing doping levels in scaled technologies [5]. The ESD problems are further aggravated by the tight design window for high-performance I/O circuits, not allowing large ESD devices to be used as protection elements [6]. This ends up reducing the number of options available to an I/O designer [7]. ESD relia- bility imposes the following constraints over I/O design [7]: 1) granularity in width and fixed length, which are imposed by some of the ESD rules, causing a tradeoff between the speed, area, and ESD performance of the I/O circuit; 2) ESD diode termination, which affects the I/O signal integrity because of large overshoots and undershoots of I/O voltage. Therefore, the overall I/O performance depends on how the I/O devices are designed and optimized while considering their susceptibility to ESD protection. Previously, mixed-signal SoC products were designed using bipolar-CMOS-DMOS (BCD) technologies [8], [9]. The trend toward lowering the system cost has favored the use of a low- cost CMOS process. It was shown that a high-voltage (HV) CMOS process can be accomplished without any additional process complexity of buried layers as in the BCD process [10]. Scaling the HV CMOS process down to the 0.13-μm node has recently been reported [11]. The published work also reports replacing the BCD process with a CMOS process in some applications that were previously dominated by the BCD technology. HV or I/O devices are used in various applications such as broadband communication, mobile chips, smart power ICs, nonvolatile memories, microelectromechanical systems (MEMSs), etc. For high-speed data transfer on a twisted-pair copper connection, a subscriber line interface circuit integrated in CMOS technology is required [12]–[14]. Power management modules such as the high-efficiency switch-mode dc–dc con- verter are critical building blocks for state-of-the-art portable applications. They are used to accurately transform a battery supply into various regulated voltages, as required by their loads [15], [16]. Charge pump circuits are used to generate dc voltages higher than the nominal power supply [17], which are used in nonvolatile flash memories [18] and MEMS [19] appli- cations. Charge pump circuits are also used in some low-voltage 0018-9383/$26.00 © 2009 IEEE