A study of placement algorithms through trial interchange of logic modules Soumitra K Nandy and L M Patnaik* Based on trial interchanges, this paper develops three algorithms for the solution of the placement problem of logic modules in a circuit. A significant decrease in the computation time of such placement algorithms can be achieved by restricting the trial interchanges to only a subset of all the modules in a circuit. The three algorithms are simulated on a DEC 1090 system in Pascal and the performance of these algorithms in terms of total wire- length and computation time is compared with the results obtained by Steinberg, for the 34-module backboard wiring problem. Performance analysis of the first two algorithms reveals that algorithms based on pairwise trial interchanges (2 interchanges) achieve a desired placement faster than the algorithms based on trial N interchanges. The first two algorithms do not perform better than Steinberg's algorithm 1, whereas the third algorithm based on trial pairwise interchange among unconnected pairs of modules (UPM) and connected pairs of modules (CPM) performs better than Steinberg's algorithm, both in terms of total wirelength (TWL) and computation time. computation time, trial interchanges, placementtechnique, logic modules Integrated circuit design consists of placing box-like rectangular blocks (called logic modules) of various dimensions in a plane and connecting them by wires according to a given set of interconnection patterns. It is here that there exists a lot of similarity among the layout diagrams of MOS ICs, gate array LSls and PCBs. The placement of components on a PCB is analogous to that of placing logic modules in a plane for an IC design. Formally the module placement problem consists of finding the optimal placement of modules in the board with respect to some norm (an objective function) on the interconnections, such as minimal weighted wirelength. Any placement technique may be categorized as one which begins with no modules assigned to locations on a rectangular array or one that starts with a required initial placement, which is then systematically improved. The former is termed as constructive initial placement and the latter as the iterative improvement placement technique. The constructive initial placement techniques have been Computer Centre, Indian Institute of Science, Bangalore -- 560 012, India. *School of Automation, Indian Institute of Science, Bangalore -- 560 012, India. shown to have relatively little impact on the quality of a final placement if followed by a suitable iterative improve- ment placement technique 2. Constructive initial placement may significantly reduce the computational cost of some placement methods, but with theavailability of fast, effective iterative improvement techniques, there is no necessity for starting with a con- structive initial placement. A detailed discussion of the many classical algorithms based on iterative improvement techniques appears in Hanan and Kurtzberg 3. A widely accepted technique in all such placement procedures is that of trial module interchange ie when a trial module inter- change results in a cost higher than the one before the inter- change, the trial interchange is rejected, otherwise the trial interchange is accepted and the placement is updated. Steinberg I observed that if from a given placement, a subset of modules which have no common signals (an electrically unconnected set of logic modules) is extracted, then the value of placing each removed module into each vacated position can usually be calculated precisely solving the assignment problems. This process is then repeated successively on other 'disjoint' subsets until no further improvement in terms of cost is found. A detailed discussion of this algorithm is given below. It has been reported 4 that the number of modules which are moved at any step is necessarily quite small (because of the 'disjoint' requirement). Also, when a signal appears on a large number of modules, the technique precludes moving more than one of them at a time. In the following sections we give detailed descriptions of algorithms PI, P2 and P3. These are followed by a section on simulation results, where the performance of each of these algorithms is compared with Steinberg's algorithm for the 34-module backboard wiring problem. STEINBERG'S ALGORITHM 1 Given a set E = {El, E2,..., En} of n elements and Ei is connected to E i by Cij wires. If Cii = O, we obtain the symmetric connection matrix C = llCo.ll. Let r points P~, P2, • • •, Pr be given, where r 1>n. If d is some metric and d~ = d(p~, p~), the matrix D = lld~ll is the metric matrix. The quantity d~ may be interpreted as the length of the wire needed to connect two elements if one is placed at p~ and other at pp. If IM denotes the set of first M positive integers, consider the set S of one-to-one mappings of I n into I r. For each s E S let N(S) denote a bounded 210 0010--4485/85/050210--05 $03.00 © 1985 Butterworth & Co (Publishers) Ltd computer-aided design