FPGA Implementation of Reed-Solomon Codes Ms. Sukruti Kaulgud Ms. Mrinmoyee Mukherjee Thakur College of Engineering and Technology Thakur College of Engineering and Technology Dept of EXTC (student) Dept of EXTC (PG-Section) Kandivli(East), Mumbai-101 Kandivli(East), Mumbai-101 +919820667085 +919324378409 sukruti.kaulgud@thakureducation.org mrinmoyeem77@rediffmail.com ABSTRACT Reed–Solomon (RS) codes are non-binary cyclic error correcting codes. They are block-based error correcting codes with a wide range of applications in digital communications and storage and are used in various applications that required robust and energy efficient transmissions. The proposed project model is FPGA implementation and performance analysis of the RS (n, k) codec architecture. The proposed model is to design RS codec to occupy the least amount of logic blocks, be fast and parameterizable. In the proposed model both encoder and decoder will be synthesized to other FPGA architectures. Categories and Subject Descriptors B.1.1 Hardware Control Design Styles General Terms Design, Experimentation, Performance Key words Reed-Solomon codes, FPGA, Encoder, Decoder. 1. INTRODUCTION In any form of data transfer, bit errors are by following factors: media defects, electronic noise, component failures, poor connections, deterioration due to age, and other factors. Error correction is the process of detecting bit errors and correcting them. Error correcting codes may be divided into the following main categories: Linear Block codes, Cyclic codes, Convolution codes, Turbo Codes. RS codes are non-binary cyclic error correcting codes. In Communication system forward error correction is a system of error correction in which systematically generated parity bits are added to the message. Before data transmission, the encoder attaches parity symbols to the data using a predetermined algorithm before transmission. At the receiving side, the decoder detects and corrects a limited predetermined number of errors occurred during transmission. Transmitting the extra parity symbols requires extra bandwidth compared to transmitting the pure data. However, transmitting additional symbols introduced by FEC is better than retransmitting the whole package when at least an error has been detected by the receiver. This FEC may be implemented in hardware or software, as the required speed and performance dictates. Quick error correction requires implementation in digital logic ( hardware), while systems with lower data rates may tolerate a software implementation. Reed- Solomon error correcting codes are implemented in hardware for quick error correction and high data rates. The optical network G.709, which has a fast transmission rate of 40 Gbps uses the RS codes as the Forward Error Correction (FEC). 1.1 Historical background In 2007 Lionel Biard and Dominique Noguet [2] described a selection method to size the parameters of a low power RS code. The paper described a FPGA implementation of the shortened RS(40,32,4) code over GF(28) using Forward Error Correction (FEC) scheme. The scheme improved communication robustness. The design by Lionel Biard and Dominique Noguet highlights the impact of code parameters (n,k,t) as well as Galois field size on the complexity and the performance of the code. It was demonstrated that low power codes can be obtained with a low error correction capability t and a high (n,k) pair. However, a shortened code, despite its reduced performance, eliminates part of the power overhead caused by on-the-fly shortening operation. In 2008 Makiko Kan, Satoshi Okada, and et el [3] implemented a soft-decision decoder of (204,188)-Reed- Solomon code, which is used widely in standards for satellite, terrestrial, and other broadcasting systems. In 2009 Joschi Brauchle and Ralf Koetter [4] presented an efficient encoder circuit for a systematic Reed– Solomon code with arbitrary parity positions. In contrast to the Reed–Solomon encoder circuits widely available today, the parity symbols produced by the designed encoder were not restricted to form a block of consecutive parity symbols at the beginning or end of the codeword, but may be spread arbitrarily within the codeword. From the general parity-check matrix, an expression for the calculation of the Reed–Solomon parity symbols at arbitrary positions within the codeword was found and an efficient hardware implementation of the proposed encoder was designed. In 2009 Petrus Mursanto [5] conducted a series of experiments to show that efficiency improvement in Galois Field (GF) operators does not directly correspond to the system performance at application level. Numerous variants of operators were formed based on various combination of operation types (multiplication, division, inverse, square), representation basis (Polynomial, Normal, Dual), and processing types (serial, parallel). Each of the variants has the most efficient form in either time (fastest) or space (smallest occupied area) when implemented in FPGA chips. In fact, GF operators are not Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ICWET’11, February 25–26, 2011, Mumbai, Maharashtra, India. Copyright 2011 ACM 978-1-60558-812-4…$ϭϬ.ϬϬ.