© 2016, IJCSE All Rights Reserved 8 International Journal of Computer Sciences and Engineering Open Access Research Paper Volume-4, Issue-12 E-ISSN: 2347-2693 Design of a Novel Ring VCO with low Phase Noise and High frequency range Maryam Taghizadeh 1 , Parisa Taghizadeh 2 , Saeid Taghizadeh 2 , Abbas Kamaly 2 , Seyed Ali Emamghorashi 2* 1 Department of Electrical Engineering, Fasa Branch, Islamic Azad University, Shiraz, Iran 2 Department of Electrical Engineering , Fasa Branch, Islamic Azad University, Shiraz, Iran Available online at: www.ijcseonline.org Received: 24/Nov/2016 Revised: 02/Dec/2016 Accepted: 18/Dec/2016 Published: 31/Dec/2016 Abstract— In this paper a ring VCO with high frequency range and low phase noise in 0.18 um CMOS technology is presented. In the proposed VCO, two techniques including current control and forward bias of body is implemented to increase the range of frequency. It is shown that forward bias of the body of control transistor cause to increase the frequency range noticeably. Moreover, by adding an inductor in the body of control transistor, the phase noise is decreased as well. The phase noise in 1 MHz offset frequency is -90 dBc/Hz and the frequency range is 2-14 GHz. Keywords— VCO, Ring, Phase noise, Frequency range 1. Introduction PLL (Phase Locked Loop) has wide range of applications in communication and wireless systems[1]. It can be used for time base generation and synchronization circuits in digital ICs as well as phase detection and demodulation in analog circuits[1]. Figure 1 shows the block diagram of a PLL circuit. The heart of a PLL is voltage controlled oscillator (VCO) that can be implemented using LC or ring oscillators [2, 3]. LC oscillators use small value of capacitor and inductor [4] which usually have low quality factor. The low quality factor causes large phase noise and narrow tuning range. Therefore, LC oscillators are mostly used in high phase noise and narrow tuning range applications[5]. Furthermore, large spiral inductors consume a large chip area that is not desirable for integration. Figure1. A typical PLL circuit block diagram Ring voltage controlled oscillators (RVCO) have lower phase noise than LC oscillators and because of the wide tuning range, they are used in PLL circuits. In addition, because of smaller chip area comparing to LC oscillators, it is easier to integrate them in a CMOS technology. A ring oscillator consists of multiple gain stages (delay cells) in a loop [4,6] as shown in Figure 2. Different delay cells have been compared in terms of different parameters such as tuning range, power dissipation and phase noise. The delay cells can be differential or single-ended units. Differential configuration is more common because of common mode noise rejection capability, but uses larger chip area and consume more power[3]. The challenges in the RVCO design are to achieve linearity of frequency modulation, low voltage and power Consumption, low phase noise and wide frequency range [7]. Figure 2 A ring oscillator consists of multiple delay cells