FPGA Implementation of CRC with Error Correction Wael M El-Medany Computer Engineering Department, College of Information Technology, University Of Bahrain, 32038 Bahrain, Email: welmedany@uob.edu.bh Abstract - This paper presents a Cyclic Redundancy Check (CRC) soft core design and its hardware implementation on Field Programmable Gate Array (FPGA). The core design includes both of the Encoder and Decoder systems to be used for the serial data transmission and reception of the Wireless Transceiver System. VHDL (VHSIC Hardware Description Language) has been used for describing the hardware of the Intellectual Property (IP) core chip. The core design has been simulated using and tested using ISim (VHDL/Verilog). Spartan 3A FPGA starter kit from Xilinx has been used for downloading the design into Xilinx Spartan 3A FPGA chip. Keywords-FPGA; CRC Code; IP Core; VLSI. I. INTRODUCTION In digital communication systems, the error detection is performed by computing checksum on the message that needs to be transmitted. The computed checksum is then concatenated to the end of the message to generate the codeword or the check sequence number to be transmitted. At the receiving end, the received word is compared with the transmitted codeword. If both are equal, then the message received is treated as error free, otherwise there is an error detected in the received word. Cyclic Redundancy Check (CRC) Code has a wide range of applications in data communications and storage devices [1-6]. Cyclic Redundancy Check (CRC) is an error-checking block code that has been used for error detection only in which the received word has to be divided by a predetermined number called the generator number. If the reminder is zero, this means that there is no error detected, for nonzero reminder, this means that there is an error detected [7-10]. Cyclic Redundancy Check (CRCs) codes are so called because the check (data verification) code is a redundancy (it adds zero information) and the al gorithm is based on cyclic codes [11]. CRC has applications also in Integrated Circuits Testing Design (ICTD), and Logical Fault Detections (LFD) [12]. In [3], Albertengo et al. derived a method for determining the logic equations for any generator polynomial. Their formalization is based on z- transform. To obtain logic equations, many polynomial divisions are needed. Thus, it is not possible to write a VHDL code that generates automatically the equations for CRC. Normally, the design of the error control decoder is more complex than the encoder. CRC when first introduced was for error detection only, it can detect single bit error; burst error with length “w”, where “w” equal to the number of bits for the Frame Check Sequence (FCS) number; and odd number of errors based on the value for the generator umber [14-15]. Further research has investigated theoretically a CRC with error correction capabilities. Shukla and Bergmann [1] failed to show their hardware implementation for CRC with one bit error correction, and the simulation for correcting the bit error. The work presented in this paper describes the VHDL implementation of a CRC Decoder that has the advantages of correcting more than one bit error. Since we are introducing the hardware implementation for error CRC with error correction, our main concern is about the design of the CRC decoder with error correcting capabilities. The error correction in CRC decoder based on the error trapping technique, which is a cyclic linear block code [16-19]. Error trapping based on, cyclic shifting the received word on the division circuit, until the error can be trapped on the parity check bits. In that case the reminder will used as the error pattern, by which we can locate and correct the detected error. The VHDL source code has been edited and synthesized using Xilinx ISE 13.1, and then simulated and tested using ISim (VHDL/Verilog). Spartan 3A FPGA starter kit from Xilinx has been used for downloading the design into Xilinx Spartan 3A FPGA chip. The design has been tested in a hardware environment for different data inputs. The materials in this article are or ganized as follows: in Section II, a brief description of the State Machine (SM) chart of CRC encoding process; the SM chart for decoding algorithm is given in Section III; the modification in the decoding algorithm for error correction will be concluded in Section IV; in Section V, the circuit design for CRC decoder will be described, as well as the top-level design the decoder; the simulation results and discussion is given in Section VI; at the end, a conclusion will be given in Section VII. II. SM CHART FOR CRC ENCODING PROCESS The encoder generates an n-bit check sequence number from the given input k-bit information. The encoding process starts by calculation the Frame Check Sequence (FCS), by dividing the information bits by the predefined generator 266 Copyright (c) IARIA, 2012. ISBN: 978-1-61208-203-5 ICWMC 2012 : The Eighth International Conference on Wireless and Mobile Communications