Scalable Run Time Reconfigurable Architecture Abdellah Touhafi, Wouter Brissinck and Erik Dirkx Erasmus Hogeschool Brussel nijverheidskaai 1701070 Brussel Belgium Vrije Universiteit Brussel Pleinlaan 2 1050 Brussel Belgium Abstract: Currently multi-FPGA reeonfigurable eomputing systems are still eommonly used for accelerating algorithms. This teehnology where acceleration is aehieved by spatial implementation of an algorithm in reeonfigurable hardware has proven to be feasible. However, the best suiting algorithms are those who are very struetured, ean benefit from deep pipelining and need only loeal eommunieation resourees. Many algorithms ean not fulfil the third requirement onee the problem size grows and multi-FPGA systems beeome neeessary. In this paper we address the emulation of a run time reeonfigurable proeessor arehiteeture, whieh seales better for this kind of eomputing problems. 1. INTRODUCTION Currently multi-Field Programmable Gate Array (FPGA) reconfigurable computing systems are still commonly used for accelerating algorithms. This technology where acceleration is achieved by spatial implementation of an algorithm in reconfigurable hardware has proven to be feasible. However, research pointed out that the application must fulfil some requirements in order to achieve a high performance. The best suiting algorithms are those who are very structured, can benefit from deep pipelining and need only local communication resources. Many algorithms can not fulfil the third requirement once the problem size grows and multi-FPGA systems become L. M. Silveira et al. (eds.), VLSI: Systems on a Chip © Springer Science+Business Media New York 2000