New Challenges on Leakage Current Improvement in Tunnel FET by Using Low-K Oxide Mahdi Vadizadeh, Benyamin Davaji, Morteza Fathipour, Dept of Electrical and Computer Engineering, University of Tehran, Tehran, Iran Vadizadeh@gmail.com, bendavaji@yahoo.com, mfathi@ut.ac.ir, Abstract In this paper, we have shown that off-state current in the Tunneling Field Effect Transistor (TFET) can be reduced dramatically by using a low-k oxide and employing gate work function engineering. In order to enhance I on /I off ratio in the TFET, the effect of second gate employing has been investigated, hence using a low-k oxide for the gate near the drain side (Gate2) resulted in omission of fringing field effects. Therefore, the leakage current is decreased. Also a work function engineering method has been employed for the gate near the source (Gate1) to further reduce the off state current. 1. Introduction Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device dimensions are aggressively scaled, down to nanometer regime. To aim of scaling achieve high or chip density, higher speed and lower operating power. However, reduction of the gate length enhances leakage current and limits the scaling of devices. To avoid this problem, it is necessary to design the devices with very low leakage current. Tunneling Field Effect Transistor (TFET) is an interesting device in that it is compatible with complimentary metal oxide semiconductor (CMOS) processing [1-3]. It provides off-state current (I off ) and on-state current (I on ) on order of fA and nA, respectively [4, 5]. Unlike the MOSFET, in a TFET, the current mechanism is BTBT and not diffusion of carriers. This causes the subthreshold slope to be smaller than 60 mv/dec at room temperature. Hence, the device operates nearly independent of temperature [6, 7]. Use of TFETs in logic gates leads to advent of CTFET and TCMOS technologies, which will reduce the chip area. For example, in comparison with conventional CMOS technology, the chip area for each transistor could be decreased between 5 to 15 percent [3].Various methods have been employed to increase I on /I off ratio. Recently K. Boucart et.all showed that by employing high k oxide the electron tunneling probability from source to channel may be increased [4]. K K Bhuwalka et.all suggested a vertical TFET and used SiGe δp + at the source end of the channel in order to apply strain. They could reach compatible I on /I off ratio [8, 9]. J. Knoch et.all improved the I on /I off ratio and subthreshold slope by employing carbon nanotube in TFET [10]. In this paper, we investigate the effect of using two gates in order to increase I on /I off ratio for the structure under investigation. We will show that by employing two gates and a low-k oxide under gate near the drain (Gate2) as well as work function engineering for the gate near the source (Gate1), I off is reduced by four orders of magnitude. In the section 2 of this paper, the operation of principle of the device is analyzed. In section 3, the structure employed as well as details of simulation are described. Section 4 is devoted to investigation of the results obtained by simulation analysis. Finally in section 5, a conclusion will be provided. 2. Operating principle The TFET is in fact p-i-n diode in witch the potential in the intrinsic region is controlled by the gate. Thus the barrier width for carriers tunneling from source to channel and traveling to drain can be modulated by the gate voltage. As shown in Fig.1 in an n-channel TFET, the p-i-n diode is reverse biased (V ds >0). Barrier height in tunneling junction is reduced by applying positive gate voltage. When barrier width becomes smaller than 10 nm, electrons can tunnel from the source valance band into the channel conduction band. Hence, tunneling current flows [1]. The energy band diagram is shown in Fig 2.a for the on state. As indicated, the on-state current mechanism is band to band tunneling (BTBT). I off is composed of both the p-i-n diode reverse biased current as well as leakage current due to electron tunneling from source to channel and, from channel to drain in off state (see the Fig 2.b). The strength of the tunneling leakage is thus dependent on V ds . Figure 1: The schematic of n-channel TFET 3. Structure and simulation parameters The proposed structure is shown in Fig.1 with Gate1 length, L 1 equal 13nm and Gate2 length, L 2 =87nm. K 1 and φ ms1 are permittivity of Gate1 oxide and difference in metal –semi conductor work function, respectively. Similarly the permittivity of the Gate2 oxide and the difference in metal – semi conductor work function are denoted by K 2 and φ ms2 , respectively. The thickness of both gate oxides, t ox = 10 nm. The source ,drain and channel doping is equal to 1× 10 20 cm - 3 , 5× 10 18 cm -3 , 1× 10 17 cm -3 , respectively. The simulation is carried out by Dessis software [11]. In this analysis, we 978-1-4244-4952-1/09/$25.00 ©2009 IEEE 136 1st Int'l Symposium on Quality Electronic Design-Asia