Information Processing Letters 82 (2002) 155–157 An exponential gap with the removal of one negation gate Shao-Chin Sung a , Keisuke Tanaka b,∗,1 a School of Information Science, Japan Advanced Institute of Science and Technology, 1-1 Asahidai Tatsunokuchi, Ishikawa 923-1292, Japan b Department of Mathematical and Computing Sciences, Tokyo Institute of Technology, 1-12-1 Ookayama Meguro-ku, Tokyo 152-8552, Japan Received 1 December 2000; received in revised form 21 June 2001 Communicated by L.A. Hemaspaandra Keywords: Computational complexity; Circuit complexity; Negation-limited circuits 1. Introduction We do not know much about the complexities of combinational circuits (i.e., circuits with AND, OR, and NEGATION gates) for explicitly defined func- tions. Even a superlinear lower bound to combina- tional circuit size is not known. On the other hand, the complexities of monotone circuits (i.e., combinational circuits without NEGATION gates) for many explic- itly defined functions are well understood. For exam- ple, exponential lower bounds to the size of monotone circuits are known [1–3]. Exponential gaps between monotone and combinational circuit complexity have also been shown [4,3], so we cannot generally derive strong lower bounds to combinational circuit complex- ity using the bounds of monotone circuit complexity. In this situation, there is no doubt that it is necessary to understand the effect of NEGATION gates in order to obtain good lower bounds to combinational circuit complexity. This motivates the study of the * Corresponding author. E-mail addresses: son@jaist.ac.jp (S.-C. Sung), keisuke@is.titech.ac.jp (K. Tanaka). 1 Work done while the author was at NTT Information Sharing Platform Laboratories. relationship between the number of NEGATION gates and combinational circuit size. 2. Definitions and preliminaries Let f be a collection of Boolean functions f 1 ,..., f m defined on {0, 1} n . We also call f an n-input m-output Boolean function. We denote by C(f ) or C(f 1 ,...,f m ) the circuit complexity of f , i.e., the size (number of gates) of the smallest circuit consisting of AND, OR, and NEGATION gates with inputs x 1 ,...,x n and outputs f 1 (x 1 ,...,x n ),...,f m (x 1 ,...,x n ). We call a circuit with no more than r NEGA- TION gates an r -circuit. We denote by C r (f ) or C r (f 1 ,...,f m ) the size of the smallest r -circuit com- puting f . If f cannot be computed with only r NEGA- TION gates, then C r (f ) is undefined. A chain C in the Boolean lattice {0, 1} n is an increasing sequence a 1 < ··· <a k ∈{0, 1} n . The decrease of f on C is the number i  k such that for some j , f j (a i -1 )>f j (a i ). We define d(f) as 0020-0190/01/$ – see front matter  2001 Elsevier Science B.V. All rights reserved. PII:S0020-0190(01)00264-2