See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/224351842 From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding Article in IEEE Transactions on Very Large Scale Integration (VLSI) Systems · February 2009 DOI: 10.1109/TVLSI.2008.2003164 · Source: IEEE Xplore CITATIONS 40 READS 58 3 authors: Olivier Muller École Nationale Supérieure d'Informatique e… 20 PUBLICATIONS 196 CITATIONS SEE PROFILE Amer Baghdadi Institut Mines-Télécom 103 PUBLICATIONS 1,046 CITATIONS SEE PROFILE Michel Jézéquel Institut Mines-Télécom 146 PUBLICATIONS 2,207 CITATIONS SEE PROFILE All content following this page was uploaded by Michel Jézéquel on 23 January 2017. The user has requested enhancement of the downloaded file. All in-text references underlined in blue are added to the original document and are linked to publications on ResearchGate, letting you access and read them immediately.