Ashraf A. Osman. Int. Journal of Engineering Research and Application www.ijera.com ISSN : 2248-9622, Vol. 7, Issue 1, ( Part -2) January 2017, pp.40-49 www.ijera.com 40 | Page Effective Approach to Extract CMOS Model Parameters Based On Published Wafer Lot Data Ashraf A. Osman 1 and Amin B. Abdel Nabi 2 1 Department of Electrical Engineering, California State University at Sacramento, Sacramento, CA, USA 2 Department of Telecommunications Eng., Al-Nileen University, Khartoum, Sudan ABSTRACT The VLSI electronic circuit designs have steadily grown in their capacity and complexity through the years. MOSIS fabrication services provide test data that designers can used to simulate their circuit designs. The provided test results are extracted from various lot wafers and BSIM3 or BSIM4 model card parameters in addition to technology parameters are provided. It may be cumbersome to ensure design functionality over the wide range of model set of parameters. In this paper, it is proposed to utilize the average model parameters to validate circuit design functionality. It can be shown through device characterization and simple circuit simulations that the average model parameters can provide a good representation of the wide range of supplied model parameters. This is specially attractive for students of circuit design classes where classroom and graduate research work were computing resources are limited. Utilizing average model parameters alleviate the need to run simulations over the large set of models from the fabrication facility. Keywords: VLSI; Design; Automation; CAD; EDA; Higher Education, Circuit; Microelectronics. I. INTRODUCTION The VLSI electronic circuit designs have steadily grown in their capacity and complexity through the years. The circuit simulation based on technology test data is a core capability to ensure quality and functionality of circuit design. Established circuit design companies are well equipped with commercial and proprietary CMOS models. However, for educational institutes specially in developing countries the needs are massive. Circuit design students will have access to only published or granted set of CMOS device parameter models. One example provider of circuit manufacturing and model parameters is the MOSIS Integrated Circuit Fabrication Service[1]. MOSIS portal online site provides access to SPICE model parameter sets extracted through testing shuttles. The ability to enable circuit simulation as part of circuit design capability is critical to the whole circuit design and automation flow as desicribed by Osman et. al. with focus on developing country higher education institutes[2]. For teaching purposes, it is normal that a semiconductor modeling or circuit design class would require students to perform simulations using various circuit simulator tools. More advanced classes or project work would require class to complete circuit design projects going over steps of designing the circuitry, validating functionality, and in certain cases submit design for fabrication and test circuit performance post design and fabrication. Such task list would constitute the normal set of requirements for graduate level of research work. The focus of this work is to scheme an approach that would enhance simulation capability for circuit design educational projects by extracting fewer set of model parameters to be used for design validity check. The approach would list technical steps to be followed to reach the minimum required parameter set that would enable circuit testing over the valid technology spectrum. It is also expected to enhance the simulation by providing a fewer set of model parameters needed for simulations by student and instructors. This approach is expected to lead to faster turn around time for school projects to complete and with more confidence on circuit simulations. Moreover, the approach would be attractive to educational firms where less number of simulations would be needed on these student projects, hence, better use of limited computational resources available to developing countries standard educational institutes. The proposed approach will be described and detailed in the following sections. It will also be run over a set of MOSIS CMOS model parameters on various technologies. RESEARCH ARTICLE OPEN ACCESS