Microelectronics Journal 38 (2007) 1150–1155 A low-power and high-gain fully integrated CMOS LNA S. Toofan Ã , A.R. Rahmati, A. Abrishamifar, G. Roientan Lahiji Electrical Engineering Department, Iran University of Science and Technology, Iran Received 10 March 2007; received in revised form 1 October 2007; accepted 2 October 2007 Available online 13 November 2007 Abstract In this paper, we present the design of a fully integrated CMOS low noise ampliﬁer (LNA) with on-chip spiral inductors in 0.18 mm CMOS technology for 2.4 GHz frequency range. Using cascode conﬁguration, lower power consumption with higher voltage and power gain are achieved. In this conﬁguration, we managed to have a good trade off among low noise, high gain, and stability. Using common- gate (CG) conﬁguration, we reduced the parasitic effects of C gd and therefore alleviated the stability and linearity of the ampliﬁer. This conﬁguration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise ﬁgure (NF), 50 O input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S 21 ), high reverse isolation (S 12 )o60 dB, while dissipating 2.7 mW at 1.8 V power supply. r 2007 Elsevier Ltd. All rights reserved. Keywords: LNA design; Low noise ampliﬁer; Low voltage design; RF CMOS 1. Introduction Low noise ampliﬁer (LNA) is one of the most important and essential block in RF receivers [1]. The rule of LNA is to provide a decent low noise ampliﬁed signal to the next stage in the circuit (e.g. mixers) from a weak input signal that usually ranges from 140 to 40 dBm, or 0.03 mV to 3 mV by introducing as little inherent noise as possible. For example, power level of the GPS signals at the receiver is normally around 130 dBm, and this amount is degraded further in the presence of physical multi-path obstructions such as buildings and trees [2,3]. Hence, having good LNA is critical for the suitable performance of the receiver in harsh communication environments. The performance requirements of RF receivers can be quite tough, when requiring good sensitivity and excellent noise factor (F) or noise ﬁgure (NF=10 log F). LNA plays a crucial role in determining the overall noise performance of the RF receivers. The common functional requirements or design parameters of an LNA are: source impedance matching, minimum noise contribution, maximum transconductance gain, and circuit stability in the corresponding frequency bands. Furthermore, the third-order input-referred inter- cept point (IIP3) of the LNA should be maximized too [4]. There have been many optimal methods for designing of GaAs LNAs, but few for CMOS LNAs [2]. CMOS Technology is deemed suitable and is the most attractive solution for low price with good performance RF receivers. Adding other requirements such as high level of integra- tion, avoiding use of external discrete components and reducing the costs, make the LNA design even more complicated [5]. The emphasis of this paper is mostly to reduce the CMOS LNA power consumption while still retaining acceptable power gain with sufﬁcient linearity, noise performance, and good input matching. Two main frequency bands (2.4 and 5 GHz) are allocated for wireless local area networks (WLAN) [6]. This paper describes the design of a fully integrated 2.4 GHz CMOS LNA and its simulation using TSMC parameters for 0.18 mm mixed- signal; model BSIM3, version 1.1 which has been modiﬁed for RF purposes. 2.4 GHz has been chosen because; it is the ISM frequency band which has been deﬁned by some IEEE standards such as IEEE 802.15.4. In this paper, we ﬁrst discuss some of our design considerations regarding ARTICLE IN PRESS www.elsevier.com/locate/mejo 0026-2692/$ - see front matter r 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2007.10.001 Ã Corresponding author. Tel.: 98 912 594 8476; fax: +98 217 724 0490. E-mail address: S_toofan@iust.ac.ir (S. Toofan).