blend devices are likely responsible for this discrep- ancy, but further investigation is needed to fully understand this effect. 25. L. S. Li, J. T. Hu, W. D. Yang, A. P. Alivisatos, Nano Lett. 1, 349 (2001). 26. B. E. McCandless, L. V. Moulton, R. W. Birkmire, Prog. Photovoltaics 5, 249 (1997). 27. These ultrathin cells exhibit suboptimal absorptivity, with average optical density of È0.7. This assumes full back contact reflection such that incident light passes through the film twice. 28. Short-circuit currents obtained under simulated AM1.5G illumination were well matched with those obtained by integrating external quantum efficiency data with the true AM1.5G solar emission spectrum (20). 29. We thank A. Radenovic, K. Sivula, U. Bach, D. Milliron, J. Wang, and S. Laubach for research support and valuable discussion. Supported by the Director, Office of Energy Research, Office of Science, Division of Materials Sciences, of the U.S. Department of Energy under contract no. DE-AC02- 05CH11231. I.G. further acknowledges the National Science Foundation for support under a Graduate Research Fellowship. Dedicated in loving memory to Benjamin Boussert, Giulia Adesso, and Jason Choy. Supporting Online Material www.sciencemag.org/cgi/content/full/310/5747/462/ DC1 Materials and Methods 25 July 2005; accepted 20 September 2005 10.1126/science.1117908 Bridging Dimensions: Demultiplexing Ultrahigh-Density Nanowire Circuits Robert Beckman, Ezekiel Johnston-Halperin, Yi Luo, Jonathan E. Green, James R. Heath* A demultiplexer is an electronic circuit designed to separate two or more combined signals. We report on a demultiplexer architecture for bridging from the submicrometer dimensions of lithographic patterning to the nanometer- scale dimensions that can be achieved through nanofabrication methods for the selective addressing of ultrahigh-density nanowire circuits. Order log 2 (N) large wires are required to address N nanowires, and the demultiplexer archi- tecture is tolerant of low-precision manufacturing. This concept is experi- mentally demonstrated on submicrometer wires and on an array of 150 silicon nanowires patterned at nanowire widths of 13 nanometers and a pitch of 34 nanometers. One of the central challenges of nanotechnol- ogy is the selective addressing of and interac- tion with individual nanostructures at high densities (i.e., densities limited only by the in- trinsic size and packing of the nanostructures). Specifically, this challenge manifests over a range of problems, including coupling of con- ventional electronics to novel nanoelectronic devices (1), addressing of single nanoparticles for applications in quantum computing (2), and construction of high-density biomolecular sensor (3, 4) circuits. For nanoelectronics, this challenge relates to the ability to address cir- cuits that have characteristic wire dimensions and pitches that are smaller than the resolution achievable through lithographic patterning. Several groups have reported on methods for fabricating ultrahigh-density nanowire arrays (4–9). Architectural concepts for meeting the chal- lenge of electrically addressing (demultiplexing) individual nanowires that are patterned at sublithographic densities should satisfy three criteria. First, the demultiplexer architecture must bridge from the micrometer or submicro- meter dimensions achievable through lithogra- phy to the few-nanometer dimensions achievable through alternative patterning methods. Second, the architecture should allow for the addressing of many nanowires with a few large wires. Third, the manufacture of the demultiplexer should be tolerant of fabrication defects. Proposed demultiplexer architectures ( 10, 11) have been based on combining crossbars (12) (lithographically patterned demultiplexing ad- dress wires crossing the nanowires) with multi- input binary tree demultiplexers (13). Binary trees, by their very nature, exhibit order 2Elog 2 (N)^ scaling, where N is the number of nanowires and 2Elog 2 (N)^ is the number of the large demultiplexing wires used to address the nanowires. Nanowire assemblies are often characterized by some randomness in organi- zation, as well as by defects such as broken or nonconducting nanowires. To compensate, the proposed schemes contain a certain amount of redundancy (extra wires). The major cost of this redundancy is that the use of additional address wires implies that certain nanowire addresses will be redundant or nonactive; circuit testing must then be carried out to determine the good addresses, and memory must be devoted to stor- ing those addresses (14). Kuekes and Williams (10) described a diode- or resistor-based decoder that uses 5Elog 2 (N)^ large microscale address wires crossing an array of N nanowires. DeHon et al.(11) described an architecture that uses no more than 2.2Elog 2 (N)^ þ 11 address wires. Their scheme is based on the field-effect gating of nanowires by the demultiplexer, and it requires control over the doping profile along the axial dimension of the nanowires. Such nanowires have been realized experimentally (15–17 ), and Lieber_s group has used them to demonstrate a demultiplexer that bridges fabri- cation methods (i.e., self-assembly versus lithographic patterning) but not length scales (18). Both schemes are based on placing con- trollable regions on the surface of the nano- wires. An individual nanowire, which is initially in the nonconducting state, will con- duct only when all of the control regions are field- or voltage-addressed; that is, it is the logical equivalent of a multi-input AND gate. Here, we describe an electric field effect– based demultiplexing scheme that is tolerant of manufacturing defects, is not seriously limited in terms of the wire size and pitch of the de- multiplexer structure, and uses 2Elog 2 (N)^ þ R microwires to address N nanowires, where R (for redundant address lines) is zero or a small integer (14). This scheme does not require control over the axial doping profile of the underlying nanowires but can take advantage of readily achieved vertical doping profiles, and it is designed to bridge length scales. It is optimized (i.e., R is small) for nanowires for which the pitch and width of the nanowire array are precisely controlled. The scheme is based on NOR logic; that is, the only nanowire that is not field-addressed is the one selected. We first illustrate the feasibility of this concept by demultiplexing an array of Si wires 200 nm wide, patterned at a pitch of 1 mm. We then extend this approach to demultiplexing an ar- ray of 150 nanowires at a pitch of 34 nm with individual wire widths of 13 nm. Finally, we identify specific materials development path- ways that should allow the full and robust realization of this architecture. The multiplexer concept is shown in Fig. 1. Here, 2 5 (0 32) nanowires are addressed with five pairs of (drawn) large wires. Note that the binary tree pattern extends above and below the nanowire array. This eases the vertical alignment requirements: As long as the multi- plexer pattern is oriented perpendicular to the nanowire array and the nanowire pitch and width dimensions are well defined, the circuit will function (14). This aspect of the architecture makes it particularly amenable to patterning methods such as nanoimprint molding (19, 20). The major cost associated with giving up vertical alignment precision is the knowledge of exactly which nanowire is selected by a given input address. For example, the binary address B10101[ used in Fig. 1 corresponds Division of Chemistry and Chemical Engineering, California Institute of Technology, MC 127-72, 1200 East California Boulevard, Pasadena, CA 91125, USA. *To whom correspondence should be addressed. E-mail: heath@caltech.edu R EPORTS www.sciencemag.org SCIENCE VOL 310 21 OCTOBER 2005 465 on January 29, 2015 www.sciencemag.org Downloaded from on January 29, 2015 www.sciencemag.org Downloaded from on January 29, 2015 www.sciencemag.org Downloaded from on January 29, 2015 www.sciencemag.org Downloaded from