288 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010 Energy and Spatial Distributions of Electron Traps Throughout SiO 2 /Al 2 O 3 Stacks as the IPD in Flash Memory Application Xue Feng Zheng, Wei Dong Zhang, Bogdan Govoreanu, Member, IEEE, Daniel Ruiz Aguado, Jian Fu Zhang, and Jan Van Houdt, Senior Member, IEEE Abstract—SiO 2 /high-κ dielectric stacks will soon replace the conventional SiO 2 -based dielectric stacks in Flash memory cells, as the thickness of SiO 2 -based stacks is approaching its funda- mental limit. The electron trap density in high-κ layers is orders of magnitude higher than that in SiO 2 , which may introduce ex- cessive leakage via trap-assisted tunneling current and become the limiting factor for the retention of memory cells. Understanding the properties of electron traps throughout the dielectric stack is essential for estimating the leakage current and for selecting materials and processes in order to reduce the leakage. However, detailed information on trap properties in the bulk of high-κ lay- ers is still missing. A recently developed two-pulse C –V measure- ment technique is used in this paper to investigate the energy and spatial distribution of electron traps throughout the SiO 2 /Al 2 O 3 dielectric stacks. Four energy regions of electron traps have been observed. The shallower traps mainly above the Si conduction band bottom E CB are found distributed across the Al 2 O 3 layer. A narrow band of traps below Si E CB with a bandwidth of about 0.1 eV can be observed near the SiO 2 /Al 2 O 3 interface. Traps in the midlevel region corresponding to Si bandgap and traps in the deeper energy region mainly below Si valence band top are also observed. The postdeposition annealing in N 2 has different impacts on the electron traps in different energy regions. Index Terms—Al 2 O 3 , electron trap, energy distribution, Flash memory, floating gate, high-κ dielectrics, interpoly dielectric (IPD) layer, pulsed C –V . I. I NTRODUCTION T HE RAPID growth of the Flash memory market has been driven by the increase of memory capacity and the de- crease of unit price, due to the continuous downscaling of Flash memory cells [1]–[4]. However, the scaling of the conventional SiO 2 -based tunnel and control dielectric layers in Flash mem- ory technology is fast approaching its limits [2], as increasing leakage current through thinner SiO 2 layers will result in a fast data loss [3]. According to the ITRS Roadmap 2007 [4], Manuscript received June 16, 2009; revised October 6, 2009. Current version published December 23, 2009. This work was supported in part by EPSRC under Grants EP/C508793/1 and EP/C508793/2 and in part by the HEFCE PRF Scheme. The review of this paper was arranged by Editor G.-T. Jeong. X. F. Zheng, W. D. Zhang, and J. F. Zhang are with the School of Engi- neering, Liverpool John Moores University, Liverpool L3 3AF, U.K. (e-mail: w.zhang@ljmu.ac.uk). B. Govoreanu and J. Van Houdt are with the RDO/PT Division, Interuniver- sity Microelectronics Center (IMEC), Leuven 3001, Belgium. D. Ruiz Aguado is with the RDO/PT Division, IMEC, Leuven 3001, Belgium, and also with the Katholieke Universiteit Leuven, Leuven 3001, Belgium. Digital Object Identifier 10.1109/TED.2009.2035193 this becomes the most pressing issue to be solved for floating- gate Flash memory. Furthermore, starting from the 45–40-nm technology generation for floating-gate Flash devices, the spac- ing between two adjacent floating gates becomes too small to allow the control gate to overlap the floating gate on the vertical sidewalls in minimum feature-sized cells [2], [3]. In order to maintain the coupling ratio, this will require a further reduction of the dielectric thickness between control and floating gates, i.e., the interpoly dielectric (IPD), which will, in turn, inevitably increase the leakage and degrade the data retention. The introduction of high-κ materials as the IPD in floating- gate Flash memory has been proposed as a potential solution [2]–[6]. Higher dielectric constant will increase the IPD ca- pacitance without reducing its physical thickness and therefore help in maintaining the coupling ratio and allow the cell size to continue downscaling. A large amount of work has been carried out to investigate the capabilities and limits of using high-κ layers to replace the conventional oxide–nitride–oxide stack by a number of research groups [6]–[12], in order to reduce the equivalent thickness of IPD from ∼15 nm to less than 10 nm. The key issues are the capabilities of the SiO 2 /high-κ layers to provide enough program/erase windows, sufficient data re- tention and endurance, and most importantly, a low leakage to guarantee the ten-year retention. It has been reported that the density of electron traps in high-κ layers is orders of magnitude higher than that in conventional SiO 2 [13]–[15], which may induce excessive low-field leakage current through trap-assisted tunneling [16]. Understanding the properties of electron traps throughout the dielectric stack is essential not only for estimating the low- field leakage current responsible for data retention but also for selecting materials and process conditions to suppress the leakage. However, detailed information on trap properties in the bulk of high-κ layers, particularly on their energy and spatial distributions, is still missing. It has also been reported that postdeposition annealing (PDA) at different temperatures significantly changes the microstructure of high-κ layers, which may, in turn, affect the properties of electron traps [17]. This offers a way for reducing electron traps in the high-κ layer through optimizing PDA temperature. There is, however, little quantitative information on how PDA affects electron traps, particularly in terms of their energy and spatial distributions. Several groups have recently used various charge-pumping (CP) methods to probe the trap distribution in high-κ layers 0018-9383/$26.00 © 2009 IEEE Authorized licensed use limited to: LIVERPOOL JOHN MOORES UNIVERSITY. Downloaded on January 28, 2010 at 10:37 from IEEE Xplore. Restrictions apply.