On-chip Non-intrusive Temperature Detection and Compensation of a Fully Integrated CMOS RF Power Amplifier Javed S Gaggatur, Immanuel Raja , Electrical Communication Engineering Indian Institute of Science Bangalore, 560012, INDIA gsjaved,immanuel@ece.iisc.ernet.in Gaurab Banerjee , Electrical Communication Engineering Indian Institute of Science Bangalore, 560012, INDIA banerjee@ece.iisc.ernet.in Abstract—A non intrusive temperature sensing based perfor- mance compensation of an integrated CMOS power amplifier is presented here. A differential-amplifier based temperature sensor, having an area of 25μm × 25μm, is used to measure the temperature around the RF circuits. The sources of temperature increase are analyzed and their contribution to self heating are presented. The effects of self heating and thermal coupling in RF circuits is demonstrated using an power amplifier. The integrated Class-E power amplifier was designed in 0.13μm CMOS Mixed Mode/RF process. The PA output variation due to self heating was reduced by 40%. The technique shows promise for compensation and correction in high frequency operating systems like millimeter-wave circuits where variations due to self- heating can vary the functional operation greatly. I. I NTRODUCTION CMOS process technology scaling coupled with the high integration capability has enabled integrated circuits (ICs) to achieve high performance and complexity applications. The increase in the performance demand has resulted in high power densities on-chip and thereby, high localized temperatures. These thermal hot spots jeopardize chip reliability by affecting the yield, performance, operation and testing. Apart from affecting the interconnects’ speed, spatial thermal variation (i.e. the temperature difference between two nodes Δ i,j T = T i - T j ) and temporal thermal variation (i.e. temperature difference for an RF circuit ΔT (Fig. 1) in a given time interval due to thermal cycles), undermine reliability and reduce the lifetime of the chip [1]. Their impact on the interconnect delay across the chip causes clock skew, resulting in timing errors. Besides their impact on reliability, thermal variations like unbalanced thermal stress across the chip can cause permanent physical damage through package fatigue. The cooling infrastructure on the IC may not be able to contain the effects on its own. An upcoming strategy for cooling solutions, easy testing and to enhance the yield is to incorporate on-chip sensors. They monitor and measure the performance of the different system-on-chip (SoC) blocks and multi-core processors, in order to perform either self-healing strategies or built-in self test (BIST) [2]–[4]. Commercial ap- plications for integrated RF transmitters contain many on-chip monitoring mechanisms like power detectors [5], oscillation Fig. 1: Self heating of the device and thermal coupling. RF Power Amplifier VGA Antenna RF Non-invasive Temparature Sensor PA Circuit Matching Output V BIAS Fig. 2: Block diagram of the fully integrated CMOS RF PA with an on-chip non-intrusive temperature detection and compensation circuit. based tests [6]–[8] and current-based sensors [9] for PVT variation compensation, output power efficiency enhancements and calibration of the RF circuits like a low noise amplifiers (LNA) and power amplifiers (PA). In this paper, we present a thermal sensor based com- pensation of a fully integrated CMOS RF power amplifiers (Fig. 2). The variation in the PA output was reduced by 40% using non-intrusive thermal sensing. The rest of the paper is organized as follows: Section II briefly introduces the problem of self heating due to thermal coupling and dynamic thermal management as a solution. Section III presents the power dissipation in a power amplifier and the effects of the currents generated. Section IV describes the circuit implementation with the experimental results in Section V. Section VI con- cludes the paper. II. THERMAL COUPLING:SELF- HEATING Transient heat flow through the silicon substrate can be modeled by an RC network using a finite difference method- ology [10]. To reduce the number of nodes in the net without