A 2x2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5dBm in 55nm CMOS Tsung-Ming Chen 1 , Wei-Chia Chan 1 , Chien-Cheng Lin 1 , Jui-Lin Hsu 1 , Wen-Kai Li 1 , Pi-An Wu 1 , Yen-Lin Huang 1 , Yen-Chuan Huang 1 , TzungChuen Tsai 1 , Po-Yu Chang 1 , Chih-Lung Chen 1 , Chih-Hou Tsai 1 , Tao-Yao Chang 1 , I-Ching Huang 1 , Wen-Hsien Chiu 1 , Chun-Hao Liao 1 , Chia-Hsin Wu 1 , and George Chien 2 1 MediaTek Inc., Hsinchu, Taiwan, 30078, R.O.C. 2 MediaTek Inc., San Jose, CA, 95134, USA Abstract — This paper describes 2x2 MIMO 802.11ac Stage 1 WiFi + BT combo SoC chip with integrated dual- band PAs, LNAs, T/R switches, as well as a power management unit. The measured RX sensitivity of OFDM54M is -77.5dBm/ -77dBm in 2.4GHz and 5GHz, respectively. With the proposed broadband TX architecture, a high output power of 17.5dBm for 802.11ac Stage 1 VHT80 256QAM was achieved, and is extendable to the upcoming 802.11ac Stage2 VHT160. The maximum throughput achieved is 580Mbps in VHT80 MCS9 two-spatial stream mode, AWGN channel, with short GI. This chip occupies 27.8mm 2 in 55nm 1P6M CMOS technology in which the MIMO WiFi RF and analog circuits occupies 7.7mm 2 . Index Terms — WiFi, IEEE 802.11ac, MIMO SoC, RF SoC. I. INTRODUCTION The rapid growth of handheld smart devices has prompted the industry to create a new WLAN standard with faster data throughput and higher capacity (MU- MIMO). Due to the limited available bandwidth in 2.4GHz ISM band, the new 802.11ac standard operates in 5GHz UNII band with more operating channels, offers greater flexibility for channel bandwidth, and is backward compatible with the previous 802.11a standards. Utilizing a wider channel bandwidth and more complex modulation scheme, the PHY data rate can reach up to 866.7Mbps in VHT80 2x2 MIMO. However, these new schemes pose stringent design challenges for the wireless system, especially for radio transceiver. The 802.11ac standard extends the channel bandwidth from traditional 20MHz to 80MHz in Stage1, and further increases to 160MHz in upcoming Stage2. With the wider bandwidth, the signal-to-noise-ratio (SNR) and EVM of receive and transmit paths have additional contributors which are generally not an issue in 20/40MHz channels. For example, Frequency Dependent IQ imbalance (FD-IQ) which is caused by the 3dB corner mismatch between the LPFs in the transceiver I/Q paths, becomes worse with a 160MHz channel BW. This FD-IQ mismatch is not only due to the finite Gain-BW product of OP-Amp, but also the process gradient effect in deep sub-micron process. In addition, the higher order 256QAM modulation (MCS9) in 802.11ac requires more stringent EVM/SNR in both TX and RX. The 802.11ac TX EVM requirement is -32dB for MCS9, which is 4dB lower than 802.11n 64QAM; the corresponding RX SNR requirement is 6dB increased. This paper describes a monolithic 2x2 MIMO 802.11ac Stage 1 Wi-Fi + BT combo SoC chip with integrated dual- band PA’s, LNA’s, T/R switches, as well as a power management unit (PMU). Shown in Fig. 1, it also includes a variety of host interfaces, such as PCI Express 2.0/USB2.0/USB3.0, to accommodate different system requirements. Fig. 1. Block diagram of SoC  978-1-4799-3864-3/14/$31.00  2014 IEEE 2014 IEEE Radio Frequency Integrated Circuits Symposium RMO4A-5 225