FPGA based chip emulation system for test development of analog and mixed signal circuits: A case study of DC–DC buck converter R. Bhattacharya a , S. Biswas b,⇑ , S. Mukhopadhyay a a Department of Electrical Engineering, Indian Institute of Technology, Kharagpur, India b Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati, India article info Article history: Received 28 October 2011 Received in revised form 16 April 2012 Accepted 30 April 2012 Available online xxxx Keywords: FPGA emulation Analog and mixed signal circuits Test development abstract Prototyping on FPGA has become a main stream verification methodology for hardware design, test development, software co-design, etc. in the area of digital VLSI. In the case of test development, FPGA serves as a virtual DUT (Design Under Test) and test patters are applied from automatic test equipment (ATE). This verifies not only the chip with design for test (DFT) circuitry and test program but also the entire test setup involving vir- tual DUT, load board, interconnections with ATE, etc. Although, FPGA based platform is used widely for test program verification of digital ICs, this technique is not used for ana- log/mixed signal (AMS) circuits because of the difficulty in implementing AMS circuits in FPGAs. This work is concerned with the development of a test emulation platform, termed as hand-in-hand test flow, of AMS circuits based on FPGA. The proposed methodology exploits fixed-point modeling and DSP implementation techniques facilitated by latest FPGAs to model the AMS circuits. The proposed hand-in-hand test flow for AMS circuits will help the test engineers to start their test plan concurrently with the design engineers and validate them much prior to the first silicon. We have illustrated the proposed scheme using the case study of a current programmed buck type switching converter on Xilinx Ò Virtex™-5 FPGA. The FPGA emulation measurement results show that performance of the emulated DC–DC buck converter (e.g., duty ratio test, line transient, load step) matches well with that of SPICE simulation. Ó 2012 Elsevier Ltd. All rights reserved. 1. Introduction Prototyping on FPGA has become a main stream verifi- cation methodology for hardware design, test develop- ment, software co-design, etc. in the area of digital VLSI. In case of traditional VLSI testing flow, test plan develop- ment (comprising test programming, load board design, ATE programming, etc.) starts near the end of the design cycle (say, after backend). At this point of design cycle most of the design parameters like number of I/Os, I/O positions, etc. are known, which are mandatory for ATE programming and load board design. Also, verification of ATE programs and load board designs cannot be done be- fore the first silicon is taped out, mounted on the load board and physically tested by applying ATE signals. In the case of digital circuits, however, ATE programs and load boards can be developed and verified without the sil- icon being taped out. The circuit can be prototyped using an FPGA which serves as a virtual DUT (Design under Test) and placed on the load board instead of the original silicon. This verifies not only the chip with design for test (DFT) circuitry and test program but also the entire test setup involving virtual DUT, load board, interconnections with ATE, etc. It is to be noted that all test parameters namely, those related to frequency may not be verified though this virtual DUT based concept because frequency of high speed ASICs may be more than that of FPGAs. However, many of the test parameters can be verified using this scheme which may help in fixing the bugs early, even before arrival 0263-2241/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.measurement.2012.04.022 ⇑ Corresponding author. Tel.: +91 9957561026. E-mail address: santoshbiswas402@yahoo.com (S. Biswas). Measurement xxx (2012) xxx–xxx Contents lists available at SciVerse ScienceDirect Measurement journal homepage: www.elsevier.com/locate/measurement Please cite this article in press as: R. Bhattacharya et al., FPGA based chip emulation system for test development of analog and mixed signal circuits: A case study of DC–DC buck converter, Measurement (2012), http://dx.doi.org/10.1016/j.measurement.2012.04.022