Thermal-aware Placement of Standard Cells and Gate Arrays: Studies and Observations Prasun Ghosal Bengal Engg. & Sc. University, India p ghosal@it.becs.ac.in Tuhina Samanta Bengal Engg. & Sc. University, India t samanta@it.becs.ac.in Hafizur Rahaman Bengal Engg. & Sc. University, India rahaman h@it.becs.ac.in Parthasarathi Dasgupta Indian Institute of Management Calcutta, India partha@iimcal.ac.in Abstract In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and relia- bility of a chip. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contributions include: (i) an algorithm for optimal placement of the gates or cells to minimize the possible occurrence of hot spots, (ii) results of sensitivity analysis of thermal characteristic of a layout with respect to the power densities of the modules in the layout, and iden- tifying three classes of modules, and (iii) an algorithm for optimal placement of modules, with minimum possible oc- currence of hot spots, and reasonable estimated intercon- nect lengths. Experimental results on randomly generated and standard benchmark instances are quite encouraging. 1 Introduction Increased technology scaling, and increased number of components in high-performance integrated circuits have resulted in greater emphasis on thermal considerations. The increasing temperature is likely to affect multiple design parameters, such as transistor delay, interconnect delay, electro-migration effects, leakage power, and of course, the reliability of a chip. With increasing chip sizes, due to increased number of components, the wire length is also likely to increase. As such, both timing control and energy consumption dominate the design process. 1 This work is supported by grants from the Department of IT, Govt. of India, New Delhi, Projects: SMDP-II and R & D in Microelectronics Moreover, for increased power consumption, under de- sign, fabrication and packaging constraints, the heat dissi- pation by the modules of the chip are usually uneven, pro- ducing hot spots. As such, physical design of a VLSI chip requires an optimal placement of the modules such that heat dissipation by these modules are evenly distributed. 1.1 Placement Problems for Standard cells and Gate Array Placement phase of VLSI design is well-researched [11], having objectives such as minimization of area and wire- length estimates, satisfying delay budgets, and so on [10, 2]. Recent challenges in the performance-driven paradigm in- clude routability of interconnects, congestion minimization, noise and crosstalk minimization, and thermal considera- tions [7, 4]. High-quality placements are essential for vari- ous VLSI design models and sizes. Standard cell placement typically involves a number of rows of cells where each cell represents a simple circuit viz. flip-flop, logic gate etc and is stored in the cell library [10]. In Gate Array placement, however, each cell is an array of transistors and can imple- ment gate or latch by interconnecting transistors. The major difference between placement of Standard cells and Gate Array is that in the former case, cells may be of different width. As such, interchange of cells without consideration of their sizes is likely to result in overlapping of cells. The latter, however, can be taken care of through efficient over- lap elimination techniques [1]. In this paper, we consider the placement of Standard cells or Gate arrays with three major objectives: (i) finding an optimal placement with minimum possible occurrence of hot spots, (ii) performing sensitivity analysis of overall thermal characteristic of a layout with respect to the power densities of the modules in the layout, and thereby identify- ing three classes of modules, (iii) finding optimal placement IEEE Computer Society Annual Symposium on VLSI 978-0-7695-3170-0/08 $25.00 © 2008 IEEE DOI 10.1109/ISVLSI.2008.37 369