IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 6, JUNE 2010 939 Layout Decomposition Approaches for Double Patterning Lithography Andrew B. Kahng, Fellow, IEEE, Chul-Hong Park, Member, IEEE, Xu Xu, Student Member, IEEE, and Hailong Yao, Member, IEEE, Abstract —In double patterning lithography (DPL) layout de- composition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using two layout decomposition approaches based on a conflict graph. First, node splitting is performed at all feasible dividing points. Then, one approach detects conflict cycles in the graph which are unresolvable for DPL coloring, and determines the coloring solution for the remaining nodes using integer linear programming (ILP). The other approach, based on a different ILP problem formulation, deletes some edges in the graph to make it two-colorable, then finds the coloring solution in the new graph. We evaluate our methods on both real and artificial 45nm testcases. Experimental results show that our proposed layout decomposition approaches effectively decompose given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout. Index Terms—Double patterning lithography (DPL), integer linear programming (ILP), layout decomposition, node splitting. I. Introduction A S MOORE’S LAW continues to drive performance and integration with smaller circuit features, lithography is pushed to new extremes. For 32 nm node patterning, though immersion ArF (IArF) is already in use, the realization of Manuscript received June 27, 2009; revised December 8, 2009. Date of current version May 21, 2010. Research at University of California at San Diego (UCSD), La Jolla, was supported in part by the Semiconductor Technology Academic Research Center. Preliminary versions of this paper appeared in [1] and [2]. Extensions beyond [1] and [2] include the minimal conflict cycle detection algorithm along with the proof of optimality, a new conflict cycle detection-based layout decomposition flow, the extension of the problem formulation to allow one feature to appear on both masks, and a new definition of the overlap length, along with new experimental results on both scaled and real layouts of different designs. This paper was recommended by Associate Editor C. J. Alpert. A. B. Kahng is with the Departments of Computer Science and Engineering, and Electrical and Computer Engineering, University of California at San Diego (UCSD), La Jolla, CA 92093-0404 USA (e-mail: abk@ucsd.edu). C.-H. Park is with Samsung Electronics Company, Seoul 137-857, Korea (e-mail: chul.h.park@samsung.com). X. Xu is with Synopsys Inc., Mountain View, CA 94043 USA (e-mail: Xu.Xu@synopsys.com). H. Yao is with the Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China (e-mail: hailongyao@tsinghua.edu.cn). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAD.2010.2048374 extreme ultraviolet (EUV) lithography still faces significant technology obstacles. As a result, double patterning lithogra- phy (DPL) technology is attracting more and more attention. 1 An EUV imaging system is composed of mirrors coated with multilayer structures designed to have high reflectivity at 13.5 nm wavelength. There are significant technical hurdles to implementation of EUV lithography in terms of mask- blank fabrication, high output power source, resist material, etc. Challenges to production use of IArF include very high- refractive index fluids (to enable NA = 1.55–1.6), and accom- panying advances in high-index resists and optical materials. DPL involves the partitioning of dense circuit patterns into two separate exposures, whereby decreased pattern density in each exposure improves resolution and depth of focus. DPL is likely to play an even more important role than previously anticipated, since the EUV adoption timeline has been delayed [8], [15]. However, DPL increases manufacturing cost in two fundamental ways: 1) reduced fab throughput by complex process flows due to double exposure patterning, and 2) tight overlay control between the two patterning exposures. There are distinct approaches to DPL, notably double patterning (DP), double exposure (DE) and spacer double patterning (SDP) [6]. In the DP approach [15], [29], the first etch step transfers the pattern of the first resist layer into an underlying hardmask [16], [20] which is not removed during the second exposure. Photoresist is re-coated on the surface of the first process for a second exposure. The second mask, having patterns separated from the first mask, is exposed and then the flow finishes up with the hardmask and resist of second exposure. Unlike the DP approach with two separate lithography/etch steps, the DE approach incorporates two lithographic exposures with only one etch step, where the image formed by the first exposure may interact with the image formed by the second exposure [7]. In the SDP approach [18], [21], the patterns for the first layer are transferred into the hardmask and then nitride spacers are formed on the sidewalls of the patterns. A spacer is formed by deposition or reaction of the film on the pattern, followed by etching to remove all the film material except for the material on the sidewalls. Then, film material between spacers produces the patterns for the second layer [19], [22]. In this paper, we focus on DP/DE 1 It is our understanding (Chul-Hong Park) that at the leading edge of technology development for logic processes, DPL is currently (November 2009) viewed as necessary at 22 nm and 20 nm, and may be extended to the 15 nm node. 0278-0070/$26.00 c  2010 IEEE