Intrinsic Small-Signal Equivalent Circuit of GaAs MESFET’s M. KAMECHE * , M. FEHAM M. MELIANI, N. BENAHMED, S. DALI * National Centre of Space Techniques, Algeria Telecom Laboratory, University of Tlemcen, Algeria Université de Tlemcen, BP 230,Chetouane, 13000 Tlemcen Tel :0 43 28 56 89, Fax : 0 43 28 56 85 e-mail : mo_kameche@yahoo.fr Abstract : Finite Element Time Domain Method is used to determine the intrinsic elements of a broad- band small-signal equivalent circuit (SSEC) of FET’s. The values of the differents elements are calculated from the Y parameters of the intrinsic MESFET, which are obtained from the Fourier analysis of the device transient reponse to voltage-step perturbations at the drain and gate electrodes. The success of this analysis depends crucially on the accuracy of the values calculated for the instantaneous currents at the electrodes during the transient. As application we have determined the SSEC for the case of a vertical drain and source contacts GaAs MESFET’s. I. INTRODUCTION Usually, the SSEC of a FET’s is designed by choosing a topology, so that each element provides a lumped approximation to some physical aspect of the device. A SSEC which is commonly accepted is formed of fifteen different frequency-independent elements: eight of them corresponding to the external parasitic effects and normally considered independent of the bias point, and the other seven describing the intrinsic behavior of the FET and dependent on the biasing conditions. In this paper we describe a theoretical procedure to calculate the intrinsic elements of the FET SSEC starting from the Y parameters obtained by using of a Finite Element Method (FEM) simulation. The FEM includes all the mechanisms relevant to the transport in small semiconductor devices (non- stationary effects, velocity overshoot, etc). For a given operating point, the Y parameters are obtained from the Fourier analysis of the device transient response to voltage-step perturbations at the drain and gate electrodes. The validity of the intrinsic SSEC proposed can be verified by checking the frequency dependence of the calculated elements. II. THEORETICAL ANALYSIS In this technique, we employ the Fourier decomposition of the FET response to transient excitations. Let us suppose that over the stationary operating point we apply a voltage-step perturbation of amplitude 'V j at electrode j, and that I i (t) is the current response at electrode i. the complex Yij parameter will be given by the relation between the Fourier components of both signals, and can be shown to be[1]:  > @       > @ dt t I t I V V I I Yij Re i i j j i i Z Z Z sin 0 0 ³ f  '  '  f  (1)  > @   > @ dt t I t I V Yij i i j Z Z Z cos Im 0 ³ f  '  (2) where I i (0) and I i (f) are the stationary currents at electrode i before and after the voltage perturbation respectively. Figure 1 shows the small-signal equivalent circuit of the intrinsic FET, where Cds, Cgs and Cgd correspond to the drain-source, gate-source and gate-drain capacitances respectively. Ri is the resistance of the ohmic channel between the source and the gate. gm 0 represents the steady-state transconductance, and W the delay time of the transistor. gds is the drain conductance. For a given bias point, the elements of this intrinsic equivalent circuit can be obtained from the complex Y parameter corresponding to that point.   j - .exp 0 ZW gm gm  2 1 Figure 1 :Small-signal equivalent circuit of the intrinsic FET