8 Iris: A Hybrid Nanophotonic Network Design for High-Performance and Low-Power on-Chip Communication ZHENG LI,MOUSTAFA MOHAMED, XI CHEN, HONGYU ZHOU, ALAN MICKELSON, LI SHANG, and MANISH VACHHARAJANI, University of Colorado at Boulder On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfers, limits the power efficiency and perfor- mance scalability of many-core chip-multiprocessor systems. This article analyzes on-chip communication challenges and studies the characteristics of existing electrical and emerging nanophotonic interconnect. Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network, is thus introduced. Iris’s circuit-switched subnetwork supports throughput-sensitive data transfer. Iris’s optical-antenna-array- based broadcast–multicast subnetwork optimizes latency-critical traffic and supports the path setup of circuit-switched communication. Overall, the proposed nanophotonic network design offers an on-chip com- munication backplane that is power efficient while demonstrating low latency and high throughput. Categories and Subject Descriptors: C.1.2 [Processor Architectures]: Multiple Data Stream Architectures (Microprocessors)—Interconnection Architectures General Terms: Design, Performance Additional Key Words and Phrases: Nanophotonics, Networks-on-chip, Optical interconnects, Interconnec- tion networks ACM Reference Format: Li, Z., Mohamed, M., Chen, X., Zhou, H., Mickelson, A., Shang, L., and Vachharajani, M. 2011. Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication. ACM J. Emerg. Technol. Comput. Syst. 7, 2, Article 8 (June 2011), 22 pages. DOI = 10.1145/1970406.1970410 http://doi.acm.org/10.1145/1970406.1970410 1. INTRODUCTION Fabrication technology scaling has steadily improved the performance and power effi- ciency of transistors. The performance and power dissipation of global metal wires have not scaled correspondingly. They are consuming an increasing portion of the overall system power budget. As a result, core-to-core communication is perceived as the major obstacle in scaling parallel program performance of many-core chip multiprocessors. To address this challenge, attention is focused on new electrical and photonic on-chip communication solutions. Packet-switched electrical interconnect fabrics, widely used in chip-to-chip multiprocessor computer systems, have been gradually adopted in application-specific multiprocessor system-on-chips and general-purpose chip-multiprocessors. As demonstrated by recent academic and industrial chip de- signs, for instance, TRIPS [Gratz et al. 2007] and Intel’s 48-core Single-Chip Cloud This work is supported by the National Science Foundation, under awards CCF-0829950 and CCF-0954157. Authors’ address: Department of Electrical, Computer, and Energy Engineering, University of Colorado at Boulder, Engineering Center 425 UCB, Boulder, CO 80309-0425; email: Zheng.li@colorado.edu. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212) 869-0481, or permissions@acm.org. © 2011 ACM 1550-4832/2011/06-ART8 $10.00 DOI 10.1145/1970406.1970410 http://doi.acm.org/10.1145/1970406.1970410 ACM Journal on Emerging Technologies in Computing Systems, Vol. 7, No. 2, Article 8, Pub. date: June 2011.