Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems * Huimei Cheng 1 , Ji Li 1 , Jeffrey Draper 1,2 , Shahin Nazarian 1 , and Yanzhi Wang 3 1 University of Southern California, Los Angeles, USA ({huimeich, jli724, shahin}@usc.edu) 2 Information Sciences Institute, Marina Del Rey, USA (draper@isi.edu) 3 Syracuse University, Syracuse, USA (ywang393@syr.edu) ABSTRACT Leakage power consumption has recently become a great concern for modern embedded systems. FinFET technolo- gies, power gating, and near- and super-threshold regimes can significantly reduce the power consumption. However, there lacks a comprehensive analysis of jointly applying the aforementioned power saving techniques. In this paper, we investigate the application of power gating to FinFET cir- cuits operating in near- and super-threshold voltage regimes for embedded system applications. A joint optimization al- gorithm is proposed to determine the width/length, position and threshold type of the sleep transistor together with the operating voltage constrained to a certain deadline, and with the goal of minimizing energy per operation. Experimental results demonstrate that the proposed algorithm achieves up to 99.9% energy reductions when compared to the near- threshold approach without power gating and 95.3% when compared to deadline-free optimization. 1. INTRODUCTION Nanoscale CMOS technology, together with wireless com- munication and sensing technologies, has made it possible to develop ubiquitous embedded systems [1]. Nevertheless, conventional CMOS technology suffers from high leakage power due to short-channel effects [2, 3]. Hence, FinFET structures, which offer lower leakage power and superior scalability, are promising candidates for bulk CMOS struc- tures beyond the 22nm technology nodes [3]. Besides device innovation, Super-Threshold (ST) and Near- Threshold (NT) regimes have proved effective for CMOS and FinFET devices in reducing both dynamic and static energy consumption [4, 5, 6]. ST circuits, for which V dd is much higher than the threshold voltage (Vt ) of transistors but lower than the standard V dd , have been reported to at- tain up to 41% energy reduction compared with the circuits using standard V dd [7]. If V dd is further reduced to the level of Vt , the circuits operate in the NT regime and can achieve more power savings [8]. However, if the V dd is too small, the leakage energy can be significantly increased, as reducing V dd below Vt extends the leaking time exponentially. Hence, there exists a minimal energy point (MEP) [9]. * H. Cheng and J. Li contributed equally to this work. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full cita- tion on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or re- publish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. GLSVLSI ’17, May 10–12, 2017, Banff, AB, Canada. c  2017 ACM. ISBN 978-1-4503-4972-7/17/05. . . $15.00. DOI: http://dx.doi.org/10.1145/3060403.3060424 Another effective low power technique is power gating (PG) where idle gates are shut down. In a PG structure, a header (or footer) sleep transistor controls the connec- tion between the supply voltage (or ground) and the virtual supply voltage (or virtual ground). The selection between header and footer sleep transistor is one design choice, con- sidering the reduced performance gap between NMOS and PMOS in advanced technology nodes [10]. Additionally, both channel length and width of the sleep transistor should be carefully determined, since a sleep transistor with a larger channel width provides more voltage swing but less energy saving, whereas the channel length significantly affects the threshold voltage (Vt ) of the sleep transistor. Many circuit level low-power techniques such as dynamic voltage scaling, NT and ST operations, clock gating and power gating [11, 12] have been applied to embedded sys- tems. However, there lacks a comprehensive PG optimiza- tion method specifically for embedded systems that are ded- icated to certain tasks, which jointly optimizes the supply voltage and the sleep transistor parameters (including posi- tion, Vt , and channel length/width) while meeting the dead- line requirement of the task. In this paper, we investigate the efficiency of PG in ST/NT regimes for embedded systems, and the objective of the optimization problem is minimizing energy per operation without deadline violation. Simulation results show that significant energy savings can be achieved after applying PG in ST/NT regimes, and the energy per operation is affected by both the sleep transistor parameters and the supply voltage. Based on the analysis, we propose an ef- ficient deadline-aware optimization algorithm, which jointly considers the sleep transistor parameters, the supply volt- age, and the deadline requirement, and automatically opti- mizes the parameter settings in an iterative manner. Ex- perimental results exhibit that the proposed deadline-aware joint algorithm achieves energy reductions up to 99.9% when compared to near-threshold approach without power-gating structures and 95.3% when compared to deadline-free opti- mization. 2. POWER GATED EMBEDDED SYSTEMS IN ST/NT REGIMES 2.1 Basics of Power Gating Technique Power gating is an efficient way to reduce static leakage. Such energy reduction is achieved by adding sleep transistors in series with the pull-up or the pull-down of the logic blocks to shut off the power supply when the circuits are idle. There are typically two operating modes in a PG circuit, namely, active mode and sleep mode. In the active mode, the voltage drop (VX) that is induced by the sleep transistor de- grades the driving capability (Vswing ) from V dd to V dd - VX.