M.Sahithi Priyanka et al. Int. Journal of Engineering Research and Application www.ijera.com ISSN : 2248-9622, Vol. 7, Issue 3, ( Part -6) March 2017, pp.71-76 www.ijera.com DOI: 10.9790/9622-0703067176 71 | Page High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach M.Sahithi Priyanka 1 , G.Manikanta 2 , K.Bhaskar 3 , A.Ganesh 4 , V.Swetha 5 1. Student of Lendi Institute of Engineering and Technology 2. Student of Lendi Institute of Engineering and Technology 3. Student of Lendi Institute of Engineering and Technology 4 .Student of Lendi Institute of Engineering and Technology 5. Assistant Professor of Lendi institute of Engineering and Technology ABSTRACT Leakage power dissipation a major concern for scaling down portable devices. Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with the LECTOR technique and observed that the proposed technique improves the performance and reduce the power dissipation. Keywords: ONOFIC, Deep sub micron, LECTOR, Leakage current. I. INTRODUCTION The design of low power circuits mainly focus on performance, power dissipation and chip area. The concentrated part in VLSI CMOS circuits is deep sub micron regime. The constraint in deep sub micron is to reduce the device dimensions leads to decrease in chip area. Supply voltage plays an important role in electronic devices to control the power consumption. By reducing supply voltage and threshold voltage we can retains the performance. Introducing new lower level technologies in integrated circuits leads to increase in power dissipation. As the technology scaling down the leakage power dissipation goes up. Several technologies have been implemented to reducing the leakage power dissipation. Kao and chandrakasan used power gating with Multi-Threshold transistors. This is the most efficient way to lowering the leakage power dissipation of a VLSI circuits in the standby state is to turn off its supply voltage. However this technique cannot be used in sequential circuits and memory cells, as it would result in loss of data stored. Self- bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. Which acts as smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. S.Narendra et al. discovered that by connecting off state transistors in series can reduce the leakage power. In this paper we are discussing Leakage control transistor (LCT) technique to reduce the power consumption and power dissipation. Moreover, for designing high performance and low power CMOS circuits a new method is implemented which is On/Off logic (ONOFIC) approach. Section II briefly describes Power dissipation in CMOS designs. Section III describes LECTOR technique to reduce leakage power. Section IV describes our proposed technique which is ONOFIC to reduce the leakage power. Section V describes results. Section VI is about conclusion. II. POWER DISSIPATION Power dissipation is a major problem in microelectronic circuit designing the, exclusively in wireless mobile applications and gadgets computing elements. This paper deals with the reduction and optimization techniques for leakage power dissipation in VLSI CMOS circuits. The causes of power dissipation in CMOS circuits are described by the given below equation (1). P=1/2.C.VDD2. f. N + I leak .VDD + QSC .VDD. f .N (1) Where P signifies the total power dissipated, VDD represents the supply voltage, and f represents the operating frequency. The first term denotes the power required for charging and discharging the circuit RESEARCH ARTICLE OPEN ACCESS